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| m68hc12 microcontrollers freescale.com mc68hc812a4 data sheet mc68hc812a4 rev. 7 05/2006
mc68hc812a4 data sheet, rev. 7 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. ? freescale semiconductor, inc., 2006. all rights reserved. mc68hc812a4 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) august, 2001 (continued on next page) 4 figure 1-3. expanded wide mode sram expansion schematic ? figure title changed from flash eeprom to sram and address line designators corrected 40 figure 1-4. expanded narrow mo de sram expansion schematic ? figure title changed from flash eeprom to sram and address line designators corrected 42 figure 8-16. chip-select control register 0 (csctl0) ? corrected reset value for cspoe (bit 5) 138 figure 10-1. clock module block diagram ? corrected e- and p-clock generator options 156 figure 11-1. pll block diagram ? revised diagram to show correct placement of divide-by-two block 170 12.11.2 timer port data direction register ? descriptive paragraph added for clarity 209 revision history mc68hc812a4 data sheet, rev. 7 4 freescale semiconductor august, 2001 (continued) 4 12.11.3 data direction register for timer port ? repetitive information removed. see 12.11.2 timer port data direction register 209 18.12 control timing ? minimum values added for pw irq and pw tim 329 18.14 non-multiplexed expansion bus timing ? table heading changed to reflect minimum and maximum values at 8 mhz 334 september, 2001 5 table 12-3. prescaler selection ? added value column and updated prescale factors 197 18.11 eeprom ch aracteristics ? corrected minimum and maximum values for programming and erase times 328 august, 2002 6 figure 1-3. expanded wide mo de sram expansion schematic ? on sheet 1 of this schematic remove d reference to resistor r2 40 figure 1-4. expanded narrow mode sram expansion schematic ? on sheet 1 of this schematic removed reference to resistor r2 42 4.6.2 external reset ? corrected reference to eight e-clock cycles to nine e-clock cycles 77 may, 2006 7 updated to meet freescale identity guidelines. throughout 1.3 ordering information ? updated table 1-1. ordering information and added figure 1-1. device numbering system . 18 figure 1-4. expanded wide mode sram ex pansion schematic (sheet 1 of 3) ? updated sheet 1 and corrected title for sheets 2 and 3. 24 figure 1-5. expanded narrow mode sram expansion schematic (sheet 1 of 3) ? updated sheet 1 and corrected title for sheets 2 and 3. 26 figure 3-9. condition code register (ccr) ? corrected reset state for bit 7. 46 table 4-1. interrupt vector map ? corrected reference to clock monitor reset. 50 4.5 resets ? reworked paragraph for clarity. 52 figure 5-1. mode register (mode) ? changed reset state designator from peripheral to special peripheral. 58 figure 10-3. clock function register map ? removed reference to special reset for the cop control register. 102 figure 10-9. cop control register (copctl) ? corrected reset states. 107 12.4.1 prescaler ? corrected number of prescaler divides. 122 figure 12-17. timer mask 2 register (tmsk2) ? corrected reset state for bit 4. 131 table 16-5. atd interrupt sources ? corrected table title. 207 18.2 functional operating range ? corrected operating temperature range entries. 222 18.10 eeprom characteristics ? corrected minimum value for minimum programming clock frequency. 226 18.11 control timing ? corrected maximum value for frequency of operation. 227 18.12 peripheral port timing ? corrected table heading. 231 19.2 package dimensions ? replaced package dimension drawing with the latest available. 237 revision history date revision level description page number(s) mc68hc812a4 data sheet, rev. 7 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 2 register block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 chapter 3 central processor unit (cpu12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 chapter 4 resets and interr upts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 chapter 5 operating modes and resource mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 chapter 6 bus contro l and input/output (i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 chapter 7 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 chapter 8 memory expansion and ch ip-select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 chapter 9 key wakeups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 chapter 10 clock module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 chapter 11 phase-lock loop (pll). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 12 standard timer module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 chapter 13 multiple serial interface (msi ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 chapter 14 serial communications in terface module (sci) . . . . . . . . . . . . . . . . . . . . . . .151 chapter 15 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 chapter 16 analog-to-digital converter (atd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 chapter 17 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 chapter 18 electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 chapter 19 mechanical specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 list of chapters mc68hc812a4 data sheet, rev. 7 6 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 chapter 2 register block 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 chapter 3 central processor unit (cpu12) 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 programming model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.1 accumulators a and b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.2 accumulator d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.3 index registers x and y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.4 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.5 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.6 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.4 data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.6 indexed addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.7 opcodes and operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 chapter 4 resets and interrupts 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2 exception priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4.1 interrupt control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4.2 highest priority i interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table of contents mc68hc812a4 data sheet, rev. 7 8 freescale semiconductor 4.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.5.1 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.5.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.5.3 cop reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.5.4 clock monitor reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.6 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.1 operating mode and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.2 clock and watchdog control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.4 parallel i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.5 central processor unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.6 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.6.7 other resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.7 interrupt recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 chapter 5 operating modes and resource mapping 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2.1 normal operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2.1.1 normal expanded wide mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2.1.2 normal expanded narrow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2.1.3 normal single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2.2 special operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2.2.1 special expanded wide mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2.2.2 special expanded narrow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2.2.3 special single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2.2.4 special peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2.3 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3 internal resource mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.4 mode and resource mapping registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.4.1 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.4.2 register initialization register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.4.3 ram initialization register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.4.4 eeprom initialization register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.4.5 miscellaneous mapping control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.5 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 chapter 6 bus control and input/output (i/o) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.2 detecting access type from external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.2 port a data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.3 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.4 port b data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 mc68hc812a4 data sheet, rev. 7 freescale semiconductor 9 6.3.5 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.6 port c data direction register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.7 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.8 port d data direction register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.9 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.10 port e data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.11 port e assignment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.12 pullup control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.13 reduced drive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 chapter 7 eeprom 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.2 eeprom programmer?s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 7.3 eeprom control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.3.1 eeprom module configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.3.2 eeprom block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.3 eeprom test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.4 eeprom programming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 chapter 8 memory expansion and chip-select 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.2 generation of chip-selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.2.1 chip-selects independent of memory expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.2.2 chip-selects used in conjunction with memory expans ion . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3 chip-select stretch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.4 memory expansion registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.4.1 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.4.2 port g data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.4.3 port f data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.4.4 port g data direction register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.4.5 data page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.4.6 program page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.4.7 extra page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.4.8 window definition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.4.9 memory expansion assignment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.5 chip-selects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.6 chip-select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.1 chip-select control register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.2 chip-select control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.6.3 chip-select stretch registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8.7 priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table of contents mc68hc812a4 data sheet, rev. 7 10 freescale semiconductor chapter 9 key wakeups 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.2 key wakeup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.2.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.2.2 port d data direction register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.2.3 port d key wakeup interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.2.4 port d key wakeup flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.2.5 port h data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.2.6 port h data direction register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.2.7 port h key wakeup interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.2.8 port h key wakeup flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.2.9 port j data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.2.10 port j data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.2.11 port j key wakeup interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.2.12 port j key wakeup flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 9.2.13 port j key wakeup polarity register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.2.14 port j pullup/pulldown select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.2.15 port j pullup/pulldown enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 chapter 10 clock module 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.2.1 clock generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 10.3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.4.1 computer operating properly (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.4.2 real-time interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.4.3 clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.4.4 peripheral clock divider chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 03 10.5 registers and reset initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.5.1 real-time interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.5.2 real-time interrupt flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 10.5.3 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.5.4 arm/reset cop timer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 chapter 11 phase-lock loop (pll) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5 registers and reset initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5.1 loop divider registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5.2 reference divider register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.5.3 clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 mc68hc812a4 data sheet, rev. 7 freescale semiconductor 11 chapter 12 standard timer module 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.4.1 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.4.4 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.4.4.1 event counter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 12.4.4.2 gated time accumulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.5 registers and reset initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.5.1 timer ic/oc select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 12.5.2 timer compare force register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 12.5.3 timer output compare 7 mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12.5.4 timer output compare 7 data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12.5.5 timer counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 12.5.6 timer system control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 27 12.5.7 timer control registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 29 12.5.8 timer control registers 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 30 12.5.9 timer mask register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.5.10 timer mask register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.5.11 timer flag register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.5.12 timer flag register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.5.13 timer channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.5.14 pulse accumulator control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.5.15 pulse accumulator flag register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 35 12.5.16 pulse accumulator counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 12.5.17 timer test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.6 external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.6.1 input capture/output compare pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.6.2 pulse accumulator pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.7 background debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.8 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.8.1 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.8.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.8.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.9 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.10 general-purpose i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.10.1 timer port data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.10.2 timer port data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 40 12.11 using the output compare function to generate a sq uare wave . . . . . . . . . . . . . . . . . . . . . 141 12.11.1 sample calculation to obtain period counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.11.2 equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 12.11.3 code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table of contents mc68hc812a4 data sheet, rev. 7 12 freescale semiconductor chapter 13 multiple serial interface (msi) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.2 sci features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.3 spi features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.4 msi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.5 msi register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.6 general-purpose i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.6.1 port s data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.6.2 port s data direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.6.3 port s pullup and reduced drive control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.6.4 port s wired-or mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 chapter 14 serial communications in terface module (sci) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 14.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.5.2 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.5.3 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.5.3.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 14.5.3.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.5.3.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 14.5.4 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5.4.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.5.4.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.5.4.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.5.4.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.5.4.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.5.4.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.5.5 single-wire operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.5.6 loop operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 14.6 register descriptions and reset initiali zation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 14.6.1 sci baud rate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 14.6.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.6.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.6.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.6.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 14.6.6 sci data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.7 external pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.7.1 txd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.7.2 rxd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mc68hc812a4 data sheet, rev. 7 freescale semiconductor 13 14.8 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.9 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.9.1 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.9.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.9.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.10 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.11 general-purpose i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.12 serial character transmission using the sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.12.1 equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.12.2 code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 chapter 15 serial peripheral interface (spi) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5.3 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.5.4 clock phase and polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.5.5 ss output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.5.6 single-wire operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.6 spi register descriptions and reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.6.1 spi control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.6.2 spi control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.6.3 spi baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.6.4 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.6.5 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.7 external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.7.1 miso (master in, slave out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.7.2 mosi (master out, slave in) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.7.3 sck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.7.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.8 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.8.1 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.8.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.8.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.9 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.10 general-purpose i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.11 synchronous character transmission using the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.11.1 equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15.11.2 code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table of contents mc68hc812a4 data sheet, rev. 7 14 freescale semiconductor chapter 16 analog-to-digital converter (atd) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.6 registers and reset initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 16.6.1 atd control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 16.6.2 atd control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 16.6.3 atd control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 16.6.4 adt control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 16.6.5 atd control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 16.6.6 atd control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 16.6.7 atd status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 16.6.8 atd test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.6.9 atd result registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.7 low-power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.7.1 run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.7.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 16.7.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.8 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.9 general-purpose ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.10 port ad data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.11 using the atd to measure a potentiometer signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.11.1 equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 16.11.2 code listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 chapter 17 development support 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 17.2 instruction queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 17.3 background debug mode (bdm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 17.3.1 bdm serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 17.3.2 enabling bdm firmware commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 17.3.3 bdm commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 17.4 bdm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 17.4.1 bdm instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 17.4.1.1 hardware command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 17.4.1.2 firmware command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 17.4.2 bdm status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 17.4.3 bdm shift register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 17.4.4 bdm address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 17.4.5 bdm ccr holding register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 20 17.5 instruction tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 mc68hc812a4 data sheet, rev. 7 freescale semiconductor 15 chapter 18 electrical characteristics 18.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.2 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 18.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 18.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 18.5 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 18.6 atd maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 18.7 atd dc electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.8 analog converter operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.9 atd ac operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.10 eeprom characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.11 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 18.12 peripheral port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 18.13 non-multiplexed expansion bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 18.14 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 chapter 19 mechanical specifications 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 19.2 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table of contents mc68hc812a4 data sheet, rev. 7 16 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 17 chapter 1 general description 1.1 introduction the mc68hc812a4 microcontroller unit (mcu) is a 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. modules include: 16-bit central processor unit (cpu12) lite integration module (lim) two asynchronous serial communications interfaces (sci0 and sci1) serial peripheral interface (spi) timer and pulse accumulator module 8-bit analog-to-digital converter (atd) 1-kbyte random-access memory (ram) 4-kbyte electrically erasable, pr ogrammable read-only memory (eeprom) memory expansion logic with chip selects, key wakeup ports, and a phase-locked loop (pll) 1.2 features features of the mc68hc812a4 include: low-power, high-speed m68hc12 cpu power-saving stop and wait modes memory: ? 1024-byte ram ? 4096-byte eeprom ? on-chip memory mapping allows expansion to more than 5-mbyte address space single-wire background debug mode non-multiplexed address and data buses seven programmable chip-selects wi th clock stretching (expanded modes) 8-channel, enhanced 16-bit timer with programmable prescaler: ? all channels configurable as i nput capture or output compare ? flexible choice of clock source 16-bit pulse accumulator real-time interrupt circuit computer operating properly (cop) watchdog clock monitor phase-locked loop (pll) general description mc68hc812a4 data sheet, rev. 7 18 freescale semiconductor two enhanced asynchronous non-return-to-zero (nrz) serial communication interfaces (sci) enhanced synchronous serial peripheral interface (spi) 8-channel, 8-bit analog-to-digital converter (atd) up to 24 key wakeup lines with interrupt capability available in 112-lead low-profile quad flat pack (lqfp) packaging 1.3 ordering information the mc68hc812a4 is available in 112-lead lo w-profile quad flat pack (lqfp) packaging. operating temperature range and voltage requireme nts are specified when ordering the mc68hc812a4 device. refer to table 1-1 for part numbers and to figure 1-1 for details of the device numbering system. figure 1-1. device numbering system evaluation boards, assemblers, compilers, and d ebuggers are available from freescale and from third-party suppliers. an up-to-date list of products t hat support the m68hc12 family of microcontrollers can be found on the world wide web at this url: http://freescale.com documents to assist in product selection are availabl e from the freescale litera ture distribution center or local freescale sales offices. table 1-1. ordering information order number temperature voltage frequency (mhz) range designator mc68hc812a4cpv8 ?40 to + 85 cc 5.0 8.0 xc68hc812a4pv5 0 to + 70 c? 3.3 5.0 m c h c 8 1 2 a 4 x xx e family package designator temperature range pb free block diagram mc68hc812a4 data sheet, rev. 7 freescale semiconductor 19 1.4 block diagram figure 1-2. block diagram v rh v rl v dda v ssa port e / pu ddre port j / pu / pd d d r j p o r t h / p u d d r h p o r t c / p u d d r c p o r t d / p u d d r d p o r t t / p u p o r t s / p u spi0 sci1 sci0 xirq irq /v pp r/w lstrb /taglo eclk ipipe0/moda ipipe1/modb arst periodic interrupt cop watchdog clock monitor interrupt block single-wire background debug module 1-kbyte sram 4-kbyte eeprom cpu12 p o r t a d d d r t tim oc7 d d r s msi d d r f p o r t f / p u d d r g p o r t g / p u d d r a p o r t a / p u d d r b p o r t b / p u lim lite integration module l m b ? l i t e m o d u l e b u s pll clock control rxd0 txd0 rxd1 txd1 sdi/miso sdo/mosi sck bkgd / taghi reset extal xtal xfc v ddpll v sspll kwj7 kwj6 kwj5 kwj4 kwj3 kwj2 kwj1 kwj0 kwh7 kwh6 kwh5 kwh4 kwh3 kwh2 kwh1 kwh0 data15 data14 data13 data12 data11 data10 data9 data8 data7/kwd7 data6/kwd6 data5/kwd5 data4/kwd4 data3/kwd3 data2/kwd2 data1/kwd1 data0/kwd0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 non-multiplexed address/data bus addr15 addr14 addr13 addr12 addr11 addr10 addr9 addr8 addr21 addr20 addr19 addr18 addr17 addr16 cs0 cs1 cs2 cs3 csd csp0 csp1 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pg5 pg4 pg3 pg2 pg1 pg0 pf6 pf5 pf4 pf3 pf2 pf1 pf0 v dd x1 v ssi x1 v ddext x3 v ssext x3 ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 pt7 pt6 pt5 pt4 pt3 pt2 pt1 pt0 ioc6 ioc5 ioc4 ioc3 ioc2 ioc1 ioc0 ioc7/pai pad7v stby pad6 pad5 pad4 pad3 pad2 pad1 pad0 a/d converter v rh v rl v dda v ssa v stby /an7 an6 an5 an4 an3 an2 an1 an0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 ss general description mc68hc812a4 data sheet, rev. 7 20 freescale semiconductor 1.5 signal descriptions note a line over a signal name indicates an active low signal. for example, reset is active high and reset is active low. the mc68hc812a4 is available in a 112-lead low-profile quad flat pack (lqfp). the pin assignments are shown in figure 1-3 . most pins perform two or more functions, as described in table 1-2 . individual ports are cross referenced in table 1-3 and table 1-4 . figure 1-3. pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 v ssx v ddx kwj0/pj0 kwj1/pj1 kwj2/pj2 kwj3/pj3 kwj4/pj4 kwj5/pj5 kwj6/pj6 kwj7/pj7 addr16/pg0 addr17/pg1 addr18/pg2 v dd v ss addr19/pg3 addr20/pg4 addr21/pg5 bkgd / taghi data0/kwd0/pd0 data1/kwd1/pd1 data2/kwd2/pd2 data3/kwd3/pd3 data4/kwd4/pd4 data5/kwd5/pd5 data6/kwd6/pd6 data7/kwd7/pd7 data8/pc0 mc68hc812a4 112-lead lqfp 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 data9/pc1 data10/pc2 data11/pc3 data12/pc4 data13/pc5 data14/pc6 data15/pc7 xirq /pe0 irq /v pp / pe1 r/w/ pe2 lstrb /taglo /pe3 reset v ssx v ddx v ddpll xfc v sspll extal xtal eclk/pe4 moda/ipipe0/pe5 modb/ipipe1/pe6 arst/pe7 addr0/pb0 addr1/pb1 addr2/pb2 addr3/pb3 addr4/pb4 ph7/kwh7 ph6/kwh6 ph5/kwh5 ph4/kwh4 v ssx v ddx ph3/kwh3 ph2/kwh2 ph1/kwh1 ph0/kwh0 pf6/csp1 pf5/csp0 pf4/csd pf3/cs3 pf2/cs2 pf1/cs1 pf0/cs0 pa7/addr15 pa6/addr14 pa5/addr13 pa4/addr12 pa3/addr11 pa2/addr10 pa1/addr9 pa0/addr8 pb7/addr7 pb6/addr6 pb5/addr5 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 pt7/ioc7/pai pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3 pt2/ioc2 pt1/ioc1 pt0/ioc0 ps7/ss ps6/sck ps5/sdo/mosi ps4/sdi/miso ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 v ssa v dda pad7/an7/v stby pad6/an6 pad5/an5 pad4/an4 pad3/an3 pad2/an2 pad1/an1 pad0/an0 v rl v rh 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 signal descriptions mc68hc812a4 data sheet, rev. 7 freescale semiconductor 21 table 1-2. pin descriptions pin port description v dd , v ss ? operating voltage and ground for the mcu (1) v rh , v rl ? reference voltages for the adc av dd , av ss ? operating voltage and ground for the adc (2) v ddpll , v sspll ? power and ground for pll clock control v stby port ad ram standby power input xtal, extal ? input pins for either a crystal or a cmos compatible clock (3) xirq pe0 asynchronous, non-maskable external interrupt request input irq pe1 asynchronous, maskable external interrupt request input with selectable falling-edge triggering or low-level triggering r/w pe2 expansion bus data direction indicator general-purpose i/o; read/write in expanded modes lstrb pe3 low byte strobe (0 = low byte valid) (4) general-purpose i/o eclk pe4 timing reference output for external bus clock (normally, half the crystal frequency) general-purpose i/o bkgd ? mode-select pin determines initial operating mode of the mcu after reset moda pe5 mode-select input determines initial operating mode of the mcu after reset (5) modb pe6 mode-select input determines initial operating mode of the mcu after reset (5) ipipe0 pe5 instruction queu e tracking signals fo r development systems ipipe1 pe6 arst pe7 alternate active-high reset input general-purpose i/o xfc ? loop filter pin for controlled damping of pll vco loop reset ? active-low bidirectional control signal; input initializes mcu to known startup state; output when cop or clock monitor causes a reset addr15?addr8 port a single-chip modes: general-purpose i/o expanded modes: external bus pins port d in narrow data bus mode: general-purpose i/o or key wakeup port addr7?addr0 port b data15?data8 port c data7?data0 port d addr21?addr16 port g memory expansion and general-purpose i/o cs3 ?cs0 ,csd , csp1 , csp0 port f chip selects general-purpose i/o bkgd ? single-wire background debug pin mode-select pin that determines special or normal operating mode after reset kwd7?kwd0 port d key wakeup pins that can generate interrupt requests on high-to-low transitions general-purpose i/o kwh7?kwh0 port h kwj7?kwj0 port j key wakeup pins that can generate interrupt requests on any transition general-purpose i/o rxd0 ps0 receive pin for sci0 txd0 ps1 transmit pin for sci0 general description mc68hc812a4 data sheet, rev. 7 22 freescale semiconductor rxd1 ps2 receive pin for sci1 txd1 ps3 transmit pin for sci1 sdi/miso ps4 master in/slave out pin for spi sdo/mosi ps5 master out/slave in pin for spi sck ps6 serial clock for spi ss ps7 slave select output for spi in master mode; slave select input in slave mode ioc7?ioc0 port t input capture or output compare channels and pulse accumulator input 1. the mcu operates from a single power supply. use the custom ary bypass techniques as very fast signal transitions occur on mcu pins. 2. separate power supply pins allow the adc power supp ly to be bypassed independently of the mcu power supply. 3. out of reset the frequency applied to extal is twice the desi red e-clock rate. on reset all device clocks are derived from the extal input frequency. xt al is the crystal output. 4. lstrb is the exclusive-nor of a0 and the internal sz8 signal. sz8 indicates the si ze 16/8 access. 5. after reset, moda and modb can be configured as inst ruction queue tracking signals ipipe0 and ipipe1 or as gener- al-purpose i/o pins. table 1-3. port descriptions port direction function port a i/o single-chip modes: general-purpose i/o expanded modes: external address bus addr15?addr8 port b i/o single-chip modes: general-purpose i/o expanded modes: external address bus addr7?addr0 port c i/o single-chip modes: general-purpose i/o expanded wide modes: external data bus data15?data8 expanded narrow modes: external data bus data15?data8/data7?data0 port d i/o single-chip and expanded narrow modes: general-purpose i/o external data bus data7?data0 in expanded wide mode (1) 1. key wakeup interrupt request can occur when an input goes from high to low. port e i/o and i (2) 2. pe1 and pe0 are input-only pins. external interrupt request inputs, mode select inputs, bus control signals general-purpose i/o port f i/o chip select general-purpose i/o port g i/o memory expansion general-purpose i/o port h i/o key wakeup (3) general-purpose i/o 3. key wakeup interrupt request can occur when an input goes from high to low. port j i/o key wakeup (4) general-purpose i/o 4. key wakeup interrupt request can occur when an input goes from high to low or from low to high. port s i/o sci and spi ports general-purpose i/o port t i/o timer port general-purpose i/o port ad i adc port general-purpose input table 1-2. pin descriptions (continued) pin port description signal descriptions mc68hc812a4 data sheet, rev. 7 freescale semiconductor 23 table 1-4. port pullup, pulldown, and reduced drive summary enable bit reduced drive control bit port name resistive input loads register (address) bit name reset state register (address) bit name reset state port a pullup pucr ($000c) pupa enabled rdriv ($000d) rdpab full drive port b pullup pucr ($000c) pupb enabled rdriv ($000d) rdpab full drive port c pullup pucr ($000c) pupc enabled rdriv ($000d) rdpc full drive port d pullup pucr ($000c) pupd enabled rdriv ($000d) rdpd full drive port e: pe7, pe3, pe2, pe0 pullup pucr ($000c) pupe enabled rdriv ($000d) rdpe full drive port e: pe1 pullup always enabled rdriv ($000d) rdpe full drive port e: pe4 none ? rdriv ($000d) rdpe full drive port e: pe6 and pe5 pulldown enabled during reset ? ? ? port f pullup pucr ($000c) pupf enabled rdriv ($000d) rdpf full drive port g pullup pucr ($000c) pupg enabled rdriv ($000d) rdpg full drive port h pullup pucr ($000c) puph enabled rdriv ($000d) rdph full drive port j pullup/down (1) 1. pullup or pulldown devices for each port j pin can be select ed with the pupsj register ($0 02d). after reset, pulldowns are selected for all port j pins but must be enabled with pulej register. pulej ($002e) pulej[7:0] disabled rdriv ($000d) rdpj full drive port s pullup sp0cr2 ($00d1) pups enabled sp0cr2 ($00d1) rds full drive port t pullup tmsk2 ($008d) pupt enabled tmsk2 ($008d) rdpt full drive port ad none ? ? bkgd pullup ? ? enabled ? ? full drive general description mc68hc812a4 data sheet, rev. 7 24 freescale semiconductor figure 1-4. expanded wide mode sram expansion schematic (sheet 1 of 3) 75 76 77 78 81 82 83 84 ph0 ph1 ph2 ph3 ph4 ph5 ph6 ph7 87 88 89 90 91 92 93 94 pad0 pad1 pad2 pad3 pad4 pad5 pad6 pad7 mc68hc812a4 u1 pad0 pad1 pad2 pad3 pad4 pad5 pad6 pad7 ph0 ph1 ph2 ph3 ph4 ph5 ph6 ph7 ph[0..7] pad[0..7] 68 69 70 71 72 73 74 pf0/cs0 pf1/cs1 pf2/cs2 pf3/cs3 pf4/csd pf5/csp0 pf6/csp1 3 4 5 6 7 8 9 10 pj0/kwj0 pj1/kwj1 pj2/kwj2 pj3/kwj3 pj5/kwj4 pj5/kwj5 pj6/kwj6 pj7/kwj7 pj0 pj1 pj2 pj3 pj4 pj5 pj6 pj7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf[0..7] pj[0..7] 105 106 107 108 109 110 111 112 pt0/ioc0 pt1/ioc1 pt2/ioc2 pt3/ioc3 pt4/ioc4 pt5/ioc5 pt6/ioc6 pt7/ioc7 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 a[0..21] pt[0..7] d[0..15] 11 12 13 16 17 18 pg0/addr16 pg1/addr17 pg2/addr18 pg3/addr19 pg4/addr20 pg5/addr21 a16 a17 a18 a19 a20 a21 52 53 54 55 56 57 58 59 pb0/addr00 pb1/addr01 pb2/addr02 pb3/addr03 pb4/addr04 pb5/addr05 pb6/addr06 pb7/addr07 a0 a1 a2 a3 a4 a5 a6 a7 20 21 22 23 24 25 26 27 pd0/kwd0/data0 pd1/kwd1/data1 pd2/kwd2/data2 pd3/kwd3/data3 pd4/kwd4/data4 pd5/kwd5/data5 pd6/kwd6/data6 pd7/kwd7/data7 d0 d1 d2 d3 d4 d5 d6 d7 28 29 30 31 32 33 34 35 pc0/data08 pc1/data09 pc2/data10 pc3/data11 pc4/data12 pc5/data13 pd6/data14 pc7/data15 d8 d9 d10 d11 d12 d13 d14 d15 60 61 62 63 64 65 66 67 pa0/addr08 pa1/addr09 pa2/addr10 pa3/addr11 pa4/addr12 pa5/addr13 pa6/addr14 pa7/addr15 a8 a9 a10 a11 a12 a13 a14 a15 97 98 99 100 101 102 103 104 ps0/rxd0 ps1/rxd0 ps2/txd1 ps3/txd12 ps4/sdi/miso ps5/sd0/mosi ps6/sck ps7/ss ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps[0..7] 19 36 37 38 39 48 49 50 51 pe0/xirq pe1/irq pe2/r/ w pe3/lstrb pe4/eclk pe5/moda pe6/modb pe7/arst pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pe[0..7] bkgd/taghi 1 41 44 43 45 40 47 46 v ssx0 v ssx1 xfc v ddpll v sspll reset xtal extal 14 15 42 79 v dd v ss v ddx0 v ddx1 4 3 sw dip-2 1 2 s1 pe5 pe6 v dd y1 c3 c4 r3 r s reset v ss v dd jp2 1 2 3 4 5 6 1 2 3 4 5 6 s2 a4_reset header 6 1 mc34064 2 3 in gnd rset c9 0.1 f c8 0.1 f c7 0.1 f c6 1.0 f v dd 4.7 k ? 4.7 k ? v dd v dd c p c s u2 v ss 4.7 k ? v dd signal descriptions mc68hc812a4 data sheet, rev. 7 freescale semiconductor 25 figure 1-4. expanded wide mode sram expansi on schematic (sheet 2 of 3) figure 1-4. expanded wide mode sram expansi on schematic (sheet 3 of 3) 27 26 25 24 21 20 19 18 a9 a10 a11 a12 a13 a14 a15 a16 a9 a10 a11 a12 a13 a14 a15 a16 d[0. . 15] 5 4 3 2 1 44 43 42 a1 a2 a3 a4 a5 a6 a7 a8 a1 a2 a3 a4 a5 a6 a7 a8 u4 idt71016 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 29 30 31 32 35 36 37 38 7 8 9 10 13 14 15 16 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 we cs ble bhe 17 16 40 39 pe2/r/w pf6/csp1 a0 pe3 v cc v ss 33 34 v cc pe[0. . 7] pf[0. . 7] a[0. . 21] 8 7 6 5 4 3 2 1 a8 a9 a10 a11 a12 a13 a14 a15 a8 a9 a10 a11 a12 a13 a14 a15 d[0. . 15] 25 24 23 22 21 20 19 18 a0 a1 a2 a3 a4 a5 a6 a7 a0 a1 a2 a3 a4 a5 a6 a7 u3 am29dl400b dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 30 32 34 36 39 41 43 45 29 31 33 35 38 40 42 44 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 reset v cc v ss v ss1 12 37 27 46 byte# we 47 11 a[0. . 21] 48 17 a16 a17 a16 a17 reset v cc oe ce ry/by 15 28 26 pf[0. . 7] pe[0. . 7] v cc r5 resistor s3 mode_select pf5/csp0 pe2/r/ w general description mc68hc812a4 data sheet, rev. 7 26 freescale semiconductor figure 1-5. expanded narrow mode sram expansion schematic (sheet 1 of 3) 75 76 77 78 81 82 83 84 ph0 ph1 ph2 ph3 ph4 ph5 ph6 ph7 87 88 89 90 91 92 93 94 pad0 pad1 pad2 pad3 pad4 pad5 pad6 pad7 mc68hc812a4 u1 pad0 pad1 pad2 pad3 pad4 pad5 pad6 pad7 ph0 ph1 ph2 ph3 ph4 ph5 ph6 ph7 ph[0..7] pad[0..7] 68 69 70 71 72 73 74 pf0/cs0 pf1/cs1 pf2/cs2 pf3/cs3 pf4/csd pf5/csp0 pf6/csp1 3 4 5 6 7 8 9 10 pj0/kwj0 pj1/kwj1 pj2/kwj2 pj3/kwj3 pj5/kwj4 pj5/kwj5 pj6/kwj6 pj7/kwj7 pj0 pj1 pj2 pj3 pj4 pj5 pj6 pj7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf[0..7] pj[0..7] 105 106 107 108 109 110 111 112 pt0/ioc0 pt1/ioc1 pt2/ioc2 pt3/ioc3 pt4/ioc4 pt5/ioc5 pt6/ioc6 pt7/ioc7 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 a[0..21] pt[0..7] d[0..15] 11 12 13 16 17 18 pg0/addr16 pg1/addr17 pg2/addr18 pg3/addr19 pg4/addr20 pg5/addr21 a16 a17 a18 a19 a20 a21 52 53 54 55 56 57 58 59 pb0/addr00 pb1/addr01 pb2/addr02 pb3/addr03 pb4/addr04 pb5/addr05 pb6/addr06 pb7/addr07 a0 a1 a2 a3 a4 a5 a6 a7 20 21 22 23 24 25 26 27 pd0/kwd0/data0 pd1/kwd1/data1 pd2/kwd2/data2 pd3/kwd3/data3 pd4/kwd4/data4 pd5/kwd5/data5 pd6/kwd6/data6 pd7/kwd7/data7 d0 d1 d2 d3 d4 d5 d6 d7 28 29 30 31 32 33 34 35 pc0/data08 pc1/data09 pc2/data10 pc3/data11 pc4/data12 pc5/data13 pd6/data14 pc7/data15 d8 d9 d10 d11 d12 d13 d14 d15 60 61 62 63 64 65 66 67 pa0/addr08 pa1/addr09 pa2/addr10 pa3/addr11 pa4/addr12 pa5/addr13 pa6/addr14 pa7/addr15 a8 a9 a10 a11 a12 a13 a14 a15 97 98 99 100 101 102 103 104 ps0/rxd0 ps1/rxd0 ps2/txd1 ps3/txd12 ps4/sdi/miso ps5/sd0/mosi ps6/sck ps7/ss ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps[0..7] 19 36 37 38 39 48 49 50 51 pe0/xirq pe1/irq pe2/r/w pe3/lstrb pe4/eclk pe5/moda pe6/modb pe7/arst pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pe[0..7] bkgd/taghi 1 41 44 43 45 40 47 46 v ssx0 v ssx1 xfc v ddpll v sspll reset xtal extal 14 15 42 79 v dd v ss v ddx0 v ddx1 4 3 sw dip-2 1 2 s1 pe5 pe6 v dd y1 c3 c4 r3 r s reset vss vdd jp2 1 2 3 4 5 6 1 2 3 4 5 6 s2 a4_reset header 6 1 mc34064 2 3 in gnd rset c9 0.1 f c8 0.1 f c7 0.1 f c6 1.0 f v dd 4.7 k ? 4.7 k ? v dd v dd c p c s u2 v ss 4.7 k ? v dd signal descriptions mc68hc812a4 data sheet, rev. 7 freescale semiconductor 27 figure 1-5. expanded narrow mode sram expansion s chematic (sheet 2 of 3) figure 1-5. expanded narrow mode sram expansion s chematic (sheet 3 of 3) 27 26 23 25 4 28 29 3 a8 a9 a10 a11 a12 a13 a14 a15 a8 a9 a10 a11 a12 a13 a14 a15 d[0. . 15] 12 11 10 9 8 7 6 5 a0 a1 a2 a3 a4 a5 a6 a7 a0 a1 a2 a3 a4 a5 a6 a7 u3 am27f010 d0 d1 d2 d3 d4 d5 d6 d7 13 14 15 17 18 19 20 21 d8 d9 d10 d11 d12 d13 d14 d15 ce oe we v pp 22 24 31 1 a[0. . 21] 2 a16 a16 pf[0. . 7] pe[0. . 7] pf5/csp0 pe2/r/w pe[0. . 7] 25 24 21 23 2 26 1 a8 a9 a10 a11 a12 a13 a14 a8 a9 a10 a11 a12 a13 a14 d[0. . 15] 10 9 8 7 6 5 4 3 a0 a1 a2 a3 a4 a5 a6 a7 a0 a1 a2 a3 a4 a5 a6 a7 u3 ds1230y d0 d1 d2 d3 d4 d5 d6 d7 11 12 13 15 16 17 18 19 d8 d9 d10 d11 d12 d13 d14 d15 ce we oe 20 27 22 a[0. . 21] pf6/csp1 pe2/r/w pf[0. . 7] general description mc68hc812a4 data sheet, rev. 7 28 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 29 chapter 2 register block 2.1 overview the register block can be mapped to any 2-kbyte boundary within the standard 64-kbyte address space by manipulating bits reg15?reg11 in the initrg register. initrg establishes the upper five bits of the register block?s 16-bit address. the register block occupies the firs t 512 bytes of the 2-kbyte block. figure 2-1 shows the default addressing. 2.2 register map addr.register name bit 7654321bit 0 $0000 port a data register (porta) see page 64. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset:00000000 $0001 port b data register (portb) see page 65. read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset:00000000 $0002 port a data direction register (ddra) see page 64. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0003 port b data direction register (ddrb) see page 65. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0004 port c data register (portc) see page 66. read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset:00000000 $0005 port d data register (portd) see page 67. read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write: reset:00000000 $0006 port c data direction register (ddrc) see page 66. read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 1 of 14) register block mc68hc812a4 data sheet, rev. 7 30 freescale semiconductor $0007 port d data direction register (ddrd) see page 67. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0008 port e data register (porte) see page 68. read: pe7 pe6 pe5 pd4 pd3 pd2 pd1 pd0 write: reset:00001000 $0009 port e data direction register (ddre) see page 68. read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000011 $000a port e assignment register (pear) see page 69. read: arsie pllte pipoe neclk lstre rdwe 0 0 write: reset:00101100 $000b mode register (mode) see page 58. read: smodn modb moda estr ivis 0 emd eme write: reset:00011011 $000c pullup control register (pucr) see page 71. read: puph pupg pupf pupe pupd puc pupb pupa write: reset:11111111 $000d reduced drive register (rdriv) see page 72. read: rdpj rdph rdpg rdpf rdpe prpd rdpc rdpab write: reset:00000000 $000e reserved rrrrrrrr $000f reserved rrrrrrrr $0010 ram initialization register (initrm) see page 60. read: ram15ram14ram13ram12ram11 0 0 0 write: reset:00001000 $0011 register initialization register (initrg) see page 59. read: reg15 reg14 reg13 reg12 reg11 0 0 0 write: reset:00000000 $0012 eeprom initialization register (initee) see page 60. read: ee15 ee14 ee13 ee12 0 0 0 eeon write: reset:00010001 $0013 miscellaneous mapping control register (misc) see page 61. read: ewdirndrc000000 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 2 of 14) register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 31 $0014 real-tme interrupt control register (rtictl) see page 105. read: rtie rswai rsbck 0 rtbyp rtr2 rtr1 rtr0 write: reset:00000000 $0015 real-time interrupt flag register (rtiflg) see page 107. read: rtif 0000000 write: reset:00000000 $0016 cop control register (copctl) see page 107. read: cme fcme fcm fcop disr cr2 cr1 cr0 write: reset:00000111 $0017 arm/reset cop register (coprst) see page 109. read:00000000 write:bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset:00000000 $0018 reserved rrrrrrrr $001d reserved rrrrrrrr $001e interrupt control register (intcr) see page 51. read: irqe irqen dly 00000 write: reset:01100000 $001f highest priority i interrupt register (hprio) see page 51. read: 1 1 psel5 psel4 psel3 psel2 psel1 0 write: reset:11110010 $0020 port d key wakeup interrupt enable register (kwied) see page 94. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0021 port d key wakeup flag register (kwifd) see page 95. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0022 reserved rrrrrrrr $0023 reserved rrrrrrrr $0024 port h data register (porth) see page 95. read: ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 write: reset:00000000 $0025 port h data direction register (ddrh) see page 96. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 3 of 14) register block mc68hc812a4 data sheet, rev. 7 32 freescale semiconductor $0026 port h key wakeup interrupt enable register (kwieh) see page 96. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0027 port h key wakeup flag register (kwifh) see page 96. read: kwifh7 kwifh6 kwifh5 kwifh4 kwifh3 kwifh2 kwifh1 kwifh0 write: reset:00000000 $0028 port j data register (portj) see page 97. read: pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 write: reset:00000000 $0029 port j data direction register (ddrj) see page 97. read: ddrj7 ddrj6 ddrj5 ddrj4 ddrj3 ddrj2 ddrj1 ddrj0 write: reset:00000000 $002a port j key wakeup interrupt enable register (kwiej) see page 97. read: kwiej7 kwiej6 kwiej5 kwiej4 kwiej3 kwiej2 kwiej1 kwiej0 write: reset:00000000 $002b port j key wakeup flag register (kwifj) see page 98. read: kwifj7 kwifj6 kwifj5 kwifj4 kwifj3 kwifj2 kwifj1 kwifj0 write: reset:00000000 $002c port j key wakeup polarity register (kpolj) see page 98. read: kpolj7 kpolj6 kpolj5 kpolj4 kpolj3 kpolj2 kpolj1 kpolj0 write: reset:00000000 $002d port j key wakeup pullup/pulldown select register (pupsj) see page 99. read: pupsj7 pupsj6 pupsj5 pupsj4 pupsj3 pupsj2 pupsj1 pupsj0 write: reset:00000000 $002e port j key wakeup pullup/pulldown enable register (pulej) see page 99. read: pulej7 pulej6 pulej5 pulej4 pulej3 pulej2 pulej1 pulej0 write: reset:00000000 $002f reserved rrrrrrrr $0030 port f data register (portf) see page 85. read: 0 pf6 pf5 pf4 pf3 pf2 pf1 pf0 write: reset:00000000 $0031 port g data register (portg) see page 85. read: 0 0 bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0032 port f data direction register (ddrf) see page 86. read: 0 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 4 of 14) register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 33 $0033 port g data direction register (ddrg) see page 86. read: 0 0 ddrg5 ddrg4 ddrg3 ddrg2 ddrg1 ddrg0 write: reset:00000000 $0034 data page register (dpage) see page 86. read: pd19 pd18 pd17 pd16 pd15 pd14 pd13 pd12 write: reset:00000000 $0035 program page register (ppage) see page 87. read: ppa21 ppa20 ppa19 ppa18 ppa17 ppa16 ppa15 ppa14 write: reset:00000000 $0036 extra page register (epage) see page 87. read: pea17 pea16 pea15 pea14 pea13 pea12 pea11 pea10 write: reset:00000000 $0037 window definition register (windef) see page 87. read: dwenpwenewen00000 write: reset:00000000 $0038 memory expansion assignment register (mxar) see page 88. read: 0 0 a21e a20e a19e a18e a17e a16e write: reset:00000000 $0039 reserved rrrrrrrr $003a reserved rrrrrrrr $003b reserved rrrrrrrr $003c chip-select control register 0 (csctl0) see page 89. read: 0 csp1e csp0e csde cs3e cs2e cs1e cs0e write: reset:00000000 $003d chip-select control register 1 (csctl1) see page 90. read: 0 csp1fl cspa21 csdhf cs3ep 000 write: reset:00000000 $003e chip-select stretch register 0 (csstr0) see page 91. read: 0 0 srp1a srp1b srp0a srp0b strda strdb write: reset:00111111 $003f chip-select stretch register 1 (csstr1) see page 91. read: str3astr3bstr2astr2bstr1astr1bstr0astr0b write: reset:00111111 $0040 loop divider register high (ldvh) see page 113. read: 0 0 0 0 ldv11 ldv10 ldv9 ldv8 write: reset:00001111 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 5 of 14) register block mc68hc812a4 data sheet, rev. 7 34 freescale semiconductor $0041 loop divider register low (ldvl) see page 113. read: ldv7 ldv6 ldv5 ldv4 ldv3 ldv2 ldv1 ldv0 write: reset:11111111 $0042 reference divider register high (rdvh) see page 114. read: 0 0 0 0 rdv11 rdv10 rdv9 rdv8 write: reset:00001111 $0043 reference divider register low (rdvl) see page 114. read: rdv7 rdv6 rdv5 rdv4 rdv3 rdv2 rdv1 rdv0 write: reset:11111111 $0044 reserved rrrrrrrr $0045 reserved rrrrrrrr $0046 reserved rrrrrrrr $0047 clock control register (clkctl) see page 114. read: lckf pllon plls bcsc bcsb bcsa mcsb mcsa write: reset:00000000 $0048 reserved rrrrrrrr $005f reserved rrrrrrrr $0060 atd control register 0 (atdctl0) see page 199. read: 00000000 write: reset:00000000 $0061 atd control register 1 (atdctl1) see page 199. read:00000000 write: reset:00000000 $0062 atd control register 2 (atdctl2) see page 200. read: adpu affc awai 000 ascie ascif write: reset:00000000 $0063 atd control register 3 (atdctl3) see page 201. read:000000 frz1 frz0 write: reset:00000000 $0064 atd control register 4 (atdctl4) see page 201. read: 0 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: reset:00000001 $0065 atd control register 5 (atdctl5) see page 202. read: 0 s8cm scan mult cd cc cb ca write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 6 of 14) register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 35 $0066 atd status register 1 (atdstat1) see page 204. read: scf 0 0 0 0 cc2 cc1 cc0 write: reset:00000000 $0067 atd status register 2 (atdstat2) see page 204. read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: reset:00000000 $0068 atd test register 1 (atdtest1) see page 205. read: sar9 sar8 sar7 sar6 sar5 sar4 sar3 sar2 write: reset:00000000 $0069 atd test register 2 (atdtest2) see page 205. read: sar1 sar0 rst tstout tst3 tst2 tst1 tst0 write: reset:00000000 $006a reserved rrrrrrrr $006e reserved rrrrrrrr $006f port ad data input register (portad) see page 207. read: pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 write: reset:00000000 $0070 atd result register 0 (adr0h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $0071 reserved rrrrrrrr $0072 atd result register 1 (adr1h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $0073 reserved rrrrrrrr $0074 atd result register 2 (adr2h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $0075 reserved rrrrrrrr $0076 atd result register 3 (adr3h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $0077 reserved rrrrrrrr addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 7 of 14) register block mc68hc812a4 data sheet, rev. 7 36 freescale semiconductor $0078 atd result register 4 (adr4h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $0079 reserved rrrrrrrr $007a atd result register 5 (adr5h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $007b reserved rrrrrrrr $007c atd result register 6 (adr6h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $007d reserved rrrrrrrr $007e atd result register 7 (adr7h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $007f reserved rrrrrrrr $0080 timer ic/oc select register (tios) see page 125. read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: reset:00000000 $0081 timer compare force register (cforc) see page 125. read: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 write: reset:00000000 $0082 timer output compare 7 mask register (oc7m) see page 126. read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: reset:00000000 $0083 timer output compare 7 data register (oc7d) see page 126. read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: reset:00000000 $0084 timer counter register high (tcnth) see page 127. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0085 timer counter register low (tcntl) see page 127. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 8 of 14) register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 37 $0086 timer system control register (tscr) see page 127. read: ten tswai tsbck tffca 0000 write: reset:00000000 $0087 reserved rrrrrrrr $0088 timer control register 1 (tctl1) see page 129. read: om7 ol7 om6 ol6 om5 ol5 om4 ol4 write: reset:00000000 $0089 timer control register 2 (tctl2) see page 129. read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write: reset:00000000 $008a timer control register 3 (tctl3) see page 130. read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: reset:00000000 $008b timer control register 4 (tctl4) see page 130. read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: reset:00000000 $008c timer mask register 1 (tmsk1) see page 130. read: c7i c6i c5i c4i c3i c2i c1i c0i write: reset:00000000 $008d timer mask register 2 (tmsk2) see page 131. read: toi 0 pupt rdpt tcre pr2 pr1 pr0 write: reset:00110000 $008e timer flag register 1 (tflg1) see page 132. read: c7fc6fc5fc4fc3fc2fc1fc0f write: reset:00000000 $008f timer flag register 2 (tflg2) see page 132. read: tof 0000000 write: reset:00000000 $0090 timer channel 0 register high (tc0h) see page 133. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0091 timer channel 0 register low (tc0l) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0092 timer channel 1 register high (tc1h) see page 133. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 9 of 14) register block mc68hc812a4 data sheet, rev. 7 38 freescale semiconductor $0093 timer channel 1 register low (tc1l) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0094 timer channel 2 register high (tc2h) see page 133. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0095 timer channel 2 register low (tc2l) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0096 timer channel 3 register high (tc3h) see page 133. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0097 timer channel 3 register low (tc3l) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $0098 timer channel 4 register high (tc4h) see page 133. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $0099 timer channel 4 register low (tc4l) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $009a timer channel 5 register high (tc5h) see page 133. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $009b timer channel 5 register low (tc5l) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $009c timer channel 6 register high (tc6h) see page 133. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $009d timer channel 6 register low (tc6l) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $009e timer channel 7 register high (tc7h) see page 133. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 10 of 14) register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 39 $009f timer channel 7 register low (tc7l) see page 133. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00a0 pulse accumulator control register (pactl) see page 134. read: 0 paen pamod pedge clk1 clk0 paovi pai write: reset:00000000 $00a1 pulse accumulator flag register (paflg) see page 135. read:bit 000000 paovf paif write: reset:00000000 $00a2 pulse accumulator counter register high (pacnth) see page 136. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $00a3 pulse accumulator counter register low (pacntl) see page 136. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00a4 reserved rrrrrrrr $00ac reserved rrrrrrrr $00ad timer test register (timtst) see page 137. read: 0 0 0 0 0 0 tcbyp pcbyp write: reset:00000000 $00ae timer port data register (portt) see page 139. read: pt7 pt6 pt5 pt4 pt3 pt2 pt1 pt0 write: reset: unaffected by reset $00af timer port data direction register (ddrt) see page 140. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $00b0 reserved rrrrrrrr $00bf reserved rrrrrrrr $00c0 sci 0 baud rate register high (sc0bdh) see page 168. read: btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 $00c1 sci 0 baud rate register low (sc0bdl) see page 168. read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 11 of 14) register block mc68hc812a4 data sheet, rev. 7 40 freescale semiconductor $00c2 sci 0 control register 1 (sc0cr1) see page 169. read: loops woms rsrc m wake ilt pe pt write: reset:00000000 $00c3 sci 0 control register 2 (sc0cr2) see page 171. read: tie tcie rie ilie te re rwu sbk write: reset:00000000 $00c4 sci 0 status register 1 (sc0sr1) see page 172. read: tdre tc rdrf idle or nf fe pf write: reset:11000000 $00c5 sci 0 status register 2 (sc0sr2) see page 173. read:0000000raf write: reset:00000000 $00c6 sci 0 data register high (sc0drh) see page 174. read: r8 t8 000000 write: reset: unaffected by reset $00c7 sci 0 data register low (sc0drl) see page 174. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $00c8 sci 1 baud rate register high (sc1bdh) see page 168. read: btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 $00c9 sci 1 baud rate register low (sc1bdl) see page 168. read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 $00ca sci 1 control register 1 (sc1cr1) see page 169. read: loops woms rsrc m wake ilt pe pt write: reset:00000000 $00cb sci 1 control register 2 (sc1cr2) see page 171. read: tie tcie rie ilie te re rwu sbk write: reset:00000000 $00cc sci 1 status register 1 (sc1sr1) see page 172. read: tdre tc rdrf idle or nf fe pf write: reset:11000000 $00cd sci 1 status register 2 (sc1sr2) see page 173. read:0000000raf write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 12 of 14) register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 41 $00ce sci 1 data register high (sc1drh) see page 174. read: r8 t8 000000 write: reset: unaffected by reset $00cf sci 1 data register low (sc1drl) see page 174. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $00d0 spi 0 control register 1 (sp0cr1) see page 186. read: spie spe swom mstr cpol cpha ssoe lsbf write: reset:00000100 $00d1 spi 0 control register 2 (sp0cr2) see page 187. read: 0 0 0 0 pups rds 0 spc0 write: reset:00001000 $00d2 spi baud rate register (sp0br) see page 188. read: 0 0 0 0 0 spr2 spr1 spr0 write: reset:00000000 $00d3 spi status register (sp0sr) see page 189. read: spif wcol 0 modf 0 0 0 0 write: reset:00000000 $00d4 reserved rrrrrrrr $00d5 spi data register (sp0dr) see page 190. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset $00d6 port s data register (ports) see page 147. read: ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 write: reset: unaffected by reset $00d7 port s data direction register (ddrs) see page 148. read: ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 write: reset:00000000 $00d8 reserved rrrrrrrr $00ef reserved rrrrrrrr $00f0 eeprom configuration register (eemcr) see page 74. read: 1 1 1 1 1 eeswai protlck eerc write: reset:11111100 $00f1 eeprom block protect register (eeprot) see page 75. read: 1 bprot6 bprot5 bprot4 bprot3 bprot2 bprot1 bprot0 write: reset:11111111 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 13 of 14) register block mc68hc812a4 data sheet, rev. 7 42 freescale semiconductor 2.3 modes of operation porta, portb, portc, and data direction regi sters ddra, ddrb, and ddrc are not in the map in expanded and peripheral modes. pear , mode, pucr, and rdriv are not in the map in peripheral mode. when emd is set: portd and ddrd are not the map in wide expan ded modes, peripheral mode, and narrow special expanded mode. porte and ddre are not in the map in peripheral mode and expanded modes. kwied and kwifd are not in the map in wide expanded modes and narrow special expanded mode. $00f2 eeprom test register (eetst) see page 75. read: eeodd eeven marg eecpd eecprd 0 eecpm 0 write: reset:00000000 $00f3 eeprom programming register (eeprog) see page 76. read: bulkp 0 0 byte row erase eelat eepgm write: reset:10000000 $00f4 reserved rrrrrrrr $01ff reserved rrrrrrrr addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected figure 2-1. register map (sheet 14 of 14) mc68hc812a4 data sheet, rev. 7 freescale semiconductor 43 chapter 3 central processor unit (cpu12) 3.1 overview the cpu12 is a high-speed, 16-bit processor unit. it ha s full 16-bit data paths and wider internal registers (up to 20 bits) for high-speed extended math instructio ns. the instruction set is a proper superset of the m68hc11instruction set. the cpu12 allows instructions with odd byte counts, including many single-byte instructions. this provides efficient use of rom s pace. an instruction queue buffers program information so the cpu always has immediate access to at least three bytes of machine code at the start of every instruction. the cpu12 also offers an ext ensive set of indexed add ressing capabilities. 3.2 programming model cpu12 registers are an integral part of the cpu and are not addressed as if they were memory locations. see figure 3-1 . figure 3-1. programming model 7 15 15 15 15 15 d x y sp pc ab n sxh i zvc 0 0 0 0 0 0 7 0 condition code register 8-bit accumulators a and b 16-bit double accumulator d (a : b) index register x index register y stack pointer program counter stop disable (ignore stop opcodes) carry overflow zero negative irq interrupt mask (disable) half-carry for bcd arithmetic xirq interrupt mask (disable) central processor unit (cpu12) mc68hc812a4 data sheet, rev. 7 44 freescale semiconductor 3.3 cpu registers this section describes the cpu registers. 3.3.1 accumulators a and b accumulators a and b are general-purpose 8-bit accumulators that contain operands and results of arithmetic calculations or data manipulations. 3.3.2 accumulator d accumulator d is the concatenation of accumulators a and b. some instructions treat the combination of these two 8-bit accumulators as a 16-bit double accumulator. bit 7654321bit 0 a7 a6 a5 a4 a3 a2 a1 a0 reset: unaffected by reset figure 3-2. accumulator a (a) bit 7654321bit 0 b7 b6 b5 b4 b3 b2 b1 b0 reset: unaffected by reset figure 3-3. accumulator b (b) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 d15 (a7) d14 (a6) d13 (a5) d12 (a4) d11 (a3) d10 (a2) d9 (a1) d8 (a0) d7 (b7) d6 (b6) d5 (b5) d4 (b4) d3 (b3) d2 (b2) d1 (b1) d0 (b0) reset: unaffected by reset figure 3-4. accumulator d (d) cpu registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 45 3.3.3 index registers x and y index registers x and y are used for indexed addressing. indexed addressing adds the value in an index register to a constant or to the value in an accu mulator to form the effective address of the operand. index registers x and y can also serve as temporary data storage locations. 3.3.4 stack pointer the stack pointer (sp) contains the last stack address used. the cpu12 supports an automatic program stack that is used to save system context during subroutine calls and interrupts. the stack pointer can also serve as a temporary data storage location or as an index register for indexed addressing. 3.3.5 program counter the program counter contains the addres s of the next instruction to be executed. the program counter can also serve as an index register in all indexed addressing modes except autoincrement and autodecrement. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0 reset: unaffected by reset figure 3-5. index register x (x) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 y15 y14 y13 y12 y11 y10 y9 y8 y7 y6 y5 y4 y3 y2 y1 y0 reset: unaffected by reset figure 3-6. index register y (y) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 reset: unaffected by reset figure 3-7. stack pointer (sp) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 reset: unaffected by reset figure 3-8. program counter (pc) central processor unit (cpu12) mc68hc812a4 data sheet, rev. 7 46 freescale semiconductor 3.3.6 condition code register s ? stop disable bit setting the s bit disables the stop instruction. x ? xirq interrupt mask bit setting the x bit masks interrupt requests from the xirq pin. h ? half-carry flag the h flag is used only for bcd arithmetic operati ons. it is set when an aba, add, or adc instruction produces a carry from bit 3 of accumulator a. the daa instruction uses the h flag and the c flag to adjust the result to correct bcd format. i ? interrupt mask bit setting the i bit disables maskable interrupt sources. n ? negative flag the n flag is set when the result of an operation is less than 0. z ? zero flag the z flag is set when the result of an operation is all 0s. v ? two?s complement overflow flag the v flag is set when a two?s complement overflow occurs. c ? carry/borrow flag the c flag is set when an addition or subtraction operation produces a carry or borrow. 3.4 data types the cpu12 supports four data types: 1. bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses a byte is eight bits wide and can be accessed at any byte location. a word is composed of two consecutive bytes with the most significant by te at the lower value address. there are no special requirements for alignment of instructions or operands. bit 7654321bit 0 sxh i nzvc reset: 1 1u1uuuu u = unaffected figure 3-9. condition code register (ccr) addressing modes mc68hc812a4 data sheet, rev. 7 freescale semiconductor 47 3.5 addressing modes addressing modes determine how the cpu accesses memory locations to be operated upon. the cpu12 includes all of the addressing modes of the m68hc11 cpu as well as several new forms of indexed addressing. table 3-1 is a summary of the available addressing modes. table 3-1. addressing mode summary addressing mode source fo rmat abbreviation description inherent inst inh operands (if any) are in cpu registers. immediate inst # opr8i or inst # opr16i imm operand is included in instruction stream. 8- or 16-bit size implied by context direct inst opr8a dir operand is the lower 8 bits of an address in the range $0000?$00ff. extended inst opr16a ext operand is a 16-bit address relative inst rel8 or inst rel16 rel an 8-bit or 16-bit relative of fset from the current pc is supplied in the instruction. indexed (5-bit offset) inst oprx5 , xysp idx 5-bit signed constant offset from x, y, sp, or pc indexed (auto pre-decrement) inst oprx3 , ?xys idx auto pre-decrement x, y, or sp by 1 ~ 8 indexed (auto pre-increment) inst oprx3 , +xys idx auto pre-increment x, y, or sp by 1 ~ 8 indexed (auto post-decrement) inst oprx3 , xys? idx auto post-decrement x, y, or sp by 1 ~ 8 indexed (auto post-increment) inst oprx3 , xys+ idx auto post-increment x, y, or sp by 1 ~ 8 indexed (accumulator offset) inst abd , xysp idx indexed with 8-bit (a or b) or 16-bit (d) accumulator offset from x, y, sp, or pc indexed (9-bit offset) inst oprx9 , xysp idx1 9-bit signed constant offset from x, y, sp, or pc (lower 8-bits of offset in one extension byte) indexed (16-bit offset) inst oprx16 , xysp idx2 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) indexed-indirect (16-bit offset) inst [ oprx16 , xysp ][idx2] pointer to operand is found at... 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) indexed-indirect (d accumulator offset) inst [d, xysp ][d,idx] pointer to operand is found at... x, y, sp, or pc plus the value in d central processor unit (cpu12) mc68hc812a4 data sheet, rev. 7 48 freescale semiconductor 3.6 indexed addressing modes the cpu12 indexed modes reduce execution time and e liminate code size penalties for using the y index register. cpu12 indexed addressing uses a postbyte pl us zero, one, or two extension bytes after the instruction opcode. the postbyte and extensions do these tasks: specify which index register is used determine whether a value in an accumulator is used as an offset enable automatic pre- or post-increment or decrement specify use of 5-bit, 9-bit, or 16-bit signed offsets 3.7 opcodes and operands the cpu12 uses 8-bit opcodes. each opcode identifies a particular instruction and associated addressing mode to the cpu. several opcodes are required to pr ovide each instruction with a range of addressing capabilities. only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers. to expand the number of opcodes, a second page is added to the opcode map. opcodes on the second page are preceded by an additional byte with the value $18. to provide additional addres sing flexibility, opcodes can also be followed by a postbyte or extension bytes. postbytes implement certain forms of i ndexed addressing, transfers, exchanges, and loop primitives. extension bytes contain additional program information such as addresses, offsets, and immediate data. table 3-2. summary of indexed operations postbyte code (xb) source code syntax comments rr: 00 = x, 01 = y, 10 = sp, 11 = pc rr0nnnnn ,r n,r ?n,r 5-bit constant offset n = ?16 to +15 r can specify x, y, sp, or pc 111rr0zs n,r ?n,r constant offset (9- or 16-bit signed) z:0 = 9-bit with sign in lsb of postbyte(s) 1 = 16-bit if z = s = 1, 16-bit offset indexed-indirect (see below) rr can specify x, y, sp, or pc 111rr011 [n,r] 16-bit offset indexed-indirect rr can specify x, y, sp, or pc rr1pnnnn n,?r n,+r n,r? n,r+ auto pre-decrement/increment or auto post-decrement/increment ; p = pre-(0) or post-(1), n = ?8 to ?1, +1 to +8 rr can specify x, y, or sp (pc not a valid choice) 111rr1aa a,r b,r d,r accumulator offset (unsigned 8-bit or 16-bit) aa:00 = a 01 = b 10 = d (16-bit) 11 = see accumulator d offset indexed-indirect rr can specify x, y, sp, or pc 111rr111 [d,r] accumulator d offset indexed-indirect rr can specify x, y, sp, or pc mc68hc812a4 data sheet, rev. 7 freescale semiconductor 49 chapter 4 resets and interrupts 4.1 introduction resets and interrupts are exceptions. each exception has a 16-bit vector that points to the memory location of the associated exception-handling routine. vectors are stored in the upper 128 bytes of the standard 64-kbyte address map. the six highest vector addresses are used for resets and non-maskable interrupt sources. the remainder of the vectors are used for maskable interrupts, and al l must be initialized to point to the address of the appropriate service routine. 4.2 exception priority a hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous requests are made. six sources are not maskable. the remaining sources are maskable and any one of them can be given priority over other maskable interrupts. the priorities of the non-maskable sources are: 1. por (power-on reset) or reset pin 2. clock monitor reset 3. cop (computer operating properly) watchdog reset 4. unimplemented instruction trap 5. software interrupt instruction (swi) 6. xirq signal (if x bit in ccr = 0) 4.3 maskable interrupts maskable interrupt sources include on -chip peripheral system s and external interrupt service requests. interrupts from these sources are recognized when the global interrupt mask bit (i) in the ccr is cleared. the default state of the i bit out of reset is 1, but it can be written at any time. interrupt sources are prioritized by default but any one maskable interrupt source may be assigned the highest priority by means of the hprio register. the re lative priorities of the other sources remain the same. an interrupt that is assigned highest priority is still subject to global masking by the i bit in the ccr or by any associated local bits. interrupt vectors are not affected by priority assignment. hprio can only be written while the i bit is set (interrupts inhibited). table 4-1 lists interrupt sources and vectors in default order of priority. resets and interrupts mc68hc812a4 data sheet, rev. 7 50 freescale semiconductor table 4-1. interrupt vector map vector address exception source flag local enable ccr mask hprio value to elevate $fffe, $ffff power-on reset ? none none ? $fffc, $fffd clock monitor reset ? cme, fcme none ? $fffa, $fffb cop reset ? cop rate selected none ? $fff8, $fff9 unimplemented instruction trap ? none none ? $fff6, $fff7 swi instruction ? none none ? $fff4, $fff5 xirq pin ? none x bit ? $fff2, $fff3 irq pin or key wakeup d ? irqen, kwied[7?0] i bit $f2 $fff0, $fff1 real-time in terrupt rtif rtie i bit $f0 $ffee, $ffef timer channel 0 c0f c0i i bit $ee $ffec, $ffed timer channel 1 c1f c1i i bit $ec $ffea, $ffeb timer channel 2 c2f c2i i bit $ea $ffe8, $ffe9 timer channel 3 c3f c3i i bit $e8 $ffe6, $ffe7 timer channel 4 c4f c4i i bit $e6 $ffe4, $ffe5 timer channel 5 c5f c5i i bit $e4 $ffe2, $ffe3 timer channel 6 c6f c6i i bit $e2 $ffe0, $ffe1 timer channel 7 c7f c7i i bit $e0 $ffde, $ffdf timer overflow tof toi i bit $de $ffdc, $ffdd pulse accumulator overflow paovf paovi i bit $dc $ffda, $ffdb pulse accumulator input edge paif pai i bit $da $ffd8, $ffd9 spi serial transfer complete mode fault spif modf spi0e i bit $d8 $ffd6, $ffd7 sci0 transmit data register empty sci0 transmission complete sci0 receive data register full sci0 receiver overrun sci0 receiver idle tdre tc rdrf or idle tie tcie rie rie ilie i bit $d6 $ffd4, $ffd5 sci1 transmit data register empty sci1 transmission complete sci1 receive data register full sci1 receiver overrun sci1 receiver idle tdre tc rdrf or idle tie tcie rie rie ilie i bit $d4 $ffd2, $ffd3 atd ascif ascie i bit $d2 $ffd0, $ffd1 key wakeup j (stop wakeup) ? kwiej[7?0] i bit $d0 $ffce, $ffcf key wakeup h (stop wakeup) ? kwieh[7?0] i bit $ce $ff80?$ffcd reserved ? ? i bit $80?$cc interrupt registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 51 4.4 interrupt registers this section describes the interrupt registers. 4.4.1 interrupt control register read: anytime write: varies from bit to bit irqe ? irq edge-sensitive-only bit irqe can be written once in normal modes. in spec ial modes, irqe can be written anytime, but the first write is ignored. 1 = irq responds only to falling edges. 0 = irq pin responds to low levels. irqen ? irq enable bit irqen can be written anytime in all modes. the irq pin has an internal pullup. 1 = irq pin and key wakeup d connected to interrupt logic 0 = irq pin and key wakeup d disconnected from interrupt logic dly ? oscillator startup delay on exit from stop mode bit dly can be written once in normal modes. in special modes, dly can be written anytime. the delay time of about 4096 cycles is based on the m-clock rate chosen. 1 = stabilization delay on exit from stop mode 0 = no stabilization delay on exit from stop mode 4.4.2 highest priority i interrupt register read: anytime write: only if i mask in ccr = 1 (interrupts inhibited) to give a maskable interrupt source highest priority, wr ite the low byte of the vector address to the hprio register. for example, writing $f0 to hprio assigns highest maskable interrupt priority to the real-time address: $001e bit 7654321bit 0 read: irqe irqen dly 00000 write: reset:01100000 = unimplemented figure 4-1. interrupt control register (intcr) address: $001f bit 7654321bit 0 read: 1 1 psel5 psel4 psel3 psel2 psel1 0 write: reset:11110010 = unimplemented figure 4-2. highest priority i interrupt register (hprio) resets and interrupts mc68hc812a4 data sheet, rev. 7 52 freescale semiconductor interrupt timer ($fff0). if an unimplemented vector address or a non-i-masked vector address (a value higher than $f2) is written, then irq is the default highest priority interrupt. 4.5 resets there are five possible sources of reset: 1. power-on reset (por) 2. external reset on the reset pin 3. reset from the alternate reset pin, arst 4. the computer operating properly (cop) reset 5. clock monitor reset note the first three reset sources all share the power-on reset vector and the last two have their own vector for a total of three possible reset vectors. entry into reset is asynchronous and does not require a clock but the mcu cannot sequence out of reset without a system clock. 4.5.1 powe r-on reset a positive transition on v dd causes a power-on reset (por). an external voltage level detector, or other external reset circuits, are the usual source of reset in a system. the por circuit only initializes internal circuitry during cold starts and cannot be used to force a reset as system voltage drops. 4.5.2 external reset the cpu distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than nine e-clock cycles after an internal device releases reset. when a reset condition is sensed, the reset pin is driven low by an internal device for about 16 e-clock cycles, then released. nine e-clock cycles later, it is sampled. if the pin is still held low, the cpu assumes that an external reset has occurred. if the pin is high, it indica tes that the reset was initiated internally by either the cop system or the clock monitor. to prevent a cop or clock monitor reset from being detected during an external reset, hold the reset pin low for at least 32 cycles. an external rc power-up delay circuit on the reset pin is not recommended since circuit charge time can cause the mcu to misinterpret the type of reset that has occurred. 4.5.3 cop reset the mcu includes a computer operating properly (cop) system to help protect against software failures. when cop is enabled, software must write $55 and $aa (in this order) to the coprst register to keep a watchdog timer from timing out. other instructions may be executed between these writes. a write of any value other than $55 or $aa or software failing to execute the sequence properly causes a cop reset to occur. 4.5.4 clock monitor reset if clock frequency falls below a predetermined limit wh en the clock monitor is enabled, a reset occurs. effects of reset mc68hc812a4 data sheet, rev. 7 freescale semiconductor 53 4.6 effects of reset when a reset occurs, mcu registers and control bits are changed to known startup states, as follows. 4.6.1 operating mode and memory map the states of the bgnd, moda, and modb pins duri ng reset determine the operating mode and default memory mapping. the smodn, moda, and modb bits in the mode register reflect the status of the mode-select inputs at the rising edge of reset. oper ating mode and default maps can subsequently be changed according to strictly defined rules. 4.6.2 clock and wa tchdog control logic reset enables the cop watchdog with the cr2?cr0 bi ts set for the longest timeout period. the clock monitor is disabled. the rtif flag is cleared and automatic hardware interrupts are masked. the rate control bits are cleared, and must be initialized before the rti system is used. the dly control bit is set to specify an oscillator startup delay upon recovery from stop mode. 4.6.3 interrupts reset initializes the hprio register with the value $f2, causing the irq pin to have the highest i bit interrupt priority. the irq pin is configured for level-sensitive operation (for wired-or systems). however, the i and x bits in th e ccr are set, masking irq and xirq interrupt requests. 4.6.4 parallel i/o if the mcu comes out of reset in an expanded mode, port a and port b are the address bus. port c and port d are the data bus. in narrow mode, port c alone is the data bus. port e pins are normally used to control the external bus. the pear register affects port e pin operation. if the mcu comes out of reset in a single-chip mode, all ports are configured as general-purpose, high-impedance inputs except in normal narrow expanded mode (nne). in nne, pe3 is configured as an output driven high. in expanded modes, pf5 is an active chip-select. 4.6.5 central processor unit after reset, the cpu fetches a vector from the appropriate address and begins executing instructions. the stack pointer and other cpu registers are indete rminate immediately after reset. the ccr x and i interrupt mask bits are set to mask any interrupt re quests. the s bit is also set to inhibit the stop instruction. 4.6.6 memory after reset, the internal register block is loca ted at $0000?$01ff and ram is at $0800?$0bff. eeprom is located at $1000?$1fff in expanded modes and at $f000?$ffff in single-chip modes. 4.6.7 other resources the timer, serial communications interface (sci), serial peripheral interface (spi), and analog-to-digital converter (atd) are off after reset. resets and interrupts mc68hc812a4 data sheet, rev. 7 54 freescale semiconductor 4.7 interrupt recognition once enabled, an interrupt request can be recognized at any time afte r the i bit in the ccr is cleared. when an interrupt request is recognized, the cpu re sponds at the completion of the instruction being executed. interrupt latency varies according to the num ber of cycles required to complete the instruction. some of the longer instructions can be interrupted and resume normally after servicing the interrupt. when the cpu begins to service an interrupt request, it: clears the instruction queue calculates the return address stacks the return address and the contents of the cpu registers as shown in table 4-2 after stacking the ccr, the cpu: sets the i bit to prevent other interrupts from disrupting the interrupt service routine sets the x bit if an xirq interrupt request is pending fetches the interrupt vector for the highest-prio rity request that was pending at the beginning of the interrupt sequence begins execution of the interrupt service routine at the location pointed to by the vector if no other interrupt request is pending at the end of the interrupt service routine, an rti instruction recovers the stacked values. program execut ion resumes program at the return address. if another interrupt request is pending at the end of an interrupt service routine, the rti instruction recovers the stacked values. however, the cpu then: adjusts the stack pointer to point aga in at the stacked ccr location, sp ? 9 fetches the vector of the pending interrupt begins execution of the interrupt service routine at the location pointed to by the vector table 4-2. stacking order on entry to interrupts memory location stacked values sp ? 2 rtn h : rtn l sp ? 4 y h : y l sp ? 6 x h : x l sp ? 8 b : a sp ? 9 ccr mc68hc812a4 data sheet, rev. 7 freescale semiconductor 55 chapter 5 operating modes and resource mapping 5.1 introduction the mcu can operate in eight different modes. ea ch mode has a different default memory map and external bus configuration. after reset, most system resources can be mapped to other addresses by writing to the appropriate control registers. 5.2 operating modes the states of the bkgd, modb, and moda pins during reset determine the operating mode after reset. the smodn, modb, and moda bits in the mode regi ster show the current operating mode and provide limited mode switching during operation. the states of the bkgd, modb, and moda pins are latched into these bits on the rising edge of the reset signal. the two basic types of operating modes are: normal modes ? some registers and bits are protected against accidental changes. special modes ? protected control registers and bits are allowed greater access for special purposes such as testing and emulation. a system development and debug feature, background d ebug mode (bdm), is available in all modes. in special single-chip mode, bdm is active immediately after reset. 5.2.1 normal operating modes these modes provide three operat ing configurations. background debugging is available in all three modes, but must first be enabled for some operati ons by means of a bdm command. bdm can then be made active by another bdm command. table 5-1. mode selection bkgd modb moda mode port a port b port c port d 0 0 0 special single-chip g.p. (1) i/o 1. g.p. = general purpose g.p. i/o g.p. i/o 0 0 1 special expanded narrow addr data g.p. i/o 0 1 0 special peripheral addr data data 0 1 1 special expanded wide addr data data 1 0 0 normal single chip g.p. i/o g.p. i/o g.p. i/o 1 0 1 normal expanded narrow addr data g.p. i/o 1 1 0 reserved (forced to peripheral) ? ? ? 1 1 1 normal expanded wide addr data data operating modes and resource mapping mc68hc812a4 data sheet, rev. 7 56 freescale semiconductor 5.2.1.1 normal expanded wide mode the 16-bit external address bus uses port a for the high byte and port b for the low byte. the 16-bit external data bus uses port c for the high byte and port d for the low byte. 5.2.1.2 normal expanded narrow mode the 16-bit external address bus uses port a for the high byte and port b for the low byte. the 8-bit external data bus uses port c. in this mode, 16-bit data is presented high byte first, followed by the low byte. the address is automatically incremented on the second cycle. 5.2.1.3 normal single-chip mode there are no external buses in normal single-chip mode. the mcu operates as a stand-alone device and all program and data resources are on-chip. port pins can be used for general-purpose i/o (input/output). 5.2.2 special operating modes special operating modes are commonly used in factory testing and system development. 5.2.2.1 special expanded wide mode this mode is for emulation of normal expanded wide mode and emulation of normal single-chip mode with a 16-bit bus. the bus-control pins of port e are all configured for their bus-control output functions rather than general-purpose i/o. 5.2.2.2 special expanded narrow mode this mode is for emulation of normal expanded narro w mode. external 16-bit data is handled as two back-to-back bus cycles, one for the high byte followed by one for the low byte. internal operations continue to use full 16-bit data paths. for development purposes, port d can be made available for visibility of 16-bit internal accesses by setting the emd and ivis control bits. 5.2.2.3 special single-chip mode this mode can be used to force the mcu to active bdm mode to allow system debug through the bkgd pin. there are no external address and data buses in this mode. the mcu operates as a stand-alone device and all program and data space are on-chip. external port pins can be used for general-purpose i/o. 5.2.2.4 special peripheral mode the cpu is not active in this mode. an external master can control on-chip peripherals for testing purposes. it is not possible to change to or from this mode without going through reset. background debugging should not be used while the mcu is in s pecial peripheral mode as internal bus conflicts between bdm and the external master can cause improper operation of both modes. 5.2.3 background debug mode background debug mode (bdm) is an auxiliary operat ing mode that is used for system development. bdm is implemented in on-chip hardware and provides a full set of debug operations. some bdm internal resource mapping mc68hc812a4 data sheet, rev. 7 freescale semiconductor 57 commands can be executed while the cpu is operatin g normally. other bdm commands are firmware based and require the bdm firmware to be enabled and active for execution. in special single-chip mode, bdm is enabled and active immediately out of reset. bdm is available in all other operating modes, but must be enabled before it can be activated. bdm should not be used in special peripheral mode because of potential bus conflicts. once enabled, background mode can be made active by a serial command sent via the bkgd pin or execution of a cpu12 bgnd instruction. while backg round mode is active, the cpu can interpret special debugging commands, and read and write cpu registers, peripheral registers, and locations in memory. while bdm is active, the cpu executes code loca ted in a small on-chip rom mapped to addresses $ff20 to $ffff, and bdm control registers are accessible at addresses $ff00 to $ff06. the bdm rom replaces the regular system vectors while bdm is ac tive. while bdm is active, the user memory from $ff00 to $ffff is not in the map except through serial bdm commands. 5.3 internal resource mapping the internal register block, ram, and eeprom have default locations within the 64-kbyte standard address space but may be reassigned to other loca tions during program execut ion by setting bits in mapping registers initrg, initrm, and initee. during normal operating modes, these registers can be written once. it is advisable to ex plicitly establish these resource lo cations during the initialization phase of program execution, even if default values are chosen, to protect the registers from inadvertent modification later. writes to the mapping registers go into effect between the cycle that follows the write and the cycle after that. to assure that there are no unintended operat ions, a write to one of these registers should be followed with a nop (no operation) instruction. if conflicts occur when mapping resources, the regist er block takes precedence over the other resources; ram or eeprom addresses occupied by the register block are not available for storage. when active, bdm rom takes precedence over other resources al though a conflict between bdm rom and register space is not possible. table 5-2 shows resource mapping precedence. all address space not used by internal resources is external memory by default. the memory expansion module manages three memory overlay windows: 1. program 2. data 3. one extra page overlay the sizes and locations of the program and data over lay windows are fixed. one of two locations can be selected for the extra page (epage). table 5-2. mapping precedence precedence resource 1 bdm rom (if active) 2 register space 3ram 4 eeprom 5 external memory operating modes and resource mapping mc68hc812a4 data sheet, rev. 7 58 freescale semiconductor 5.4 mode and resour ce mapping registers this section describes the mode and resource mapping registers. 5.4.1 mode register mode controls the mcu operating mode and various confi guration options. this register is not in the map in peripheral mode. read: anytime write: varies from bit to bit smodn, modb, and moda ? mode select special, b, and a bits these bits show the current operating mode and reflect the status of the bkgd, modb, and moda input pins at the rising edge of reset. smodn can be written only if smodn = 0 (in special modes) but the first write is ignored. modb and moda may be written once if smodn = 1; anytime if smodn = 0, except that special peripheral and reserved modes cannot be selected. estr ? e-clock stretch enable bit estr determines if the e-clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. 1 = e stretches high during exter nal access cycles and low during non-visible internal accesses. 0 = e never stretches (always free running). normal modes: write once special modes: write anytime ivis ? internal visibility bit ivis determines whether internal addr, data, r/w , and lstrb signals can be seen on the external bus during accesses to internal locations. if this bit is set in special narrow mode and emd = 1 when an internal access occurs, the data appears wide on port c and port d. this allows for emulation. visibility is not available when the par t is operating in a single-chip mode. 1 = internal bus operations are visible on external bus. 0 = internal bus operations are not visible on external bus. address: $000b bit 7654321bit 0 read: smodn modb moda estr ivis 0 emd eme write: reset states special single-chip:00011011 special expanded narrow:00111011 special peripheral:01011011 special expanded wide: 0 1111011 normal single-chip:10010000 normal expanded narrow:10110000 normal expanded wide: 1 1110000 figure 5-1. mode register (mode) mode and resource mapping registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 59 normal modes: write once special modes: write anytime except the first time emd ? emulate port d bit this bit only has meaning in special expanded narrow mode. in expanded wide modes and special peripheral m ode, portd, ddrd, kwied, and kwifd are removed from the memory map regardless of the state of this bit. in single-chip modes and normal expanded narrow mode, portd, ddrd, kwied, and kwifd are in the memory map regardless of the state of this bit. 1 = if in special expanded narrow mode, portd, ddrd, kwied, and kwifd are removed from the memory map. removing the registers from the map allows the user to emulate the function of these registers externally. 0 = portd, ddrd, kwied, and kwifd are in the memory map. normal modes: write once special modes: write anytime except the first time eme ? emulate port e bit in single-chip mode, porte and ddre are always in the map regardless of the state of this bit. 1 = if in an expanded mode, porte and ddre are removed from the internal memory map. removing the registers from the map allows the us er to emulate the function of these registers externally. 0 = porte and ddre in the memory map normal modes: write once special modes: write anytime except the first time 5.4.2 register initialization register after reset, the 512-byte register block resides at location $0000 but can be reassigned to any 2-kbyte boundary within the standard 64-kbyte address space. mapping of internal registers is controlled by five bits in the initrg register. the register block occupies the first 512 bytes of the 2-kbyte block. read: anytime write: once in normal modes; anytime in special modes reg15?reg11 ? register position bits these bits specify the upper five bi ts of the 16-bit register address. address: $0011 bit 7654321bit 0 read: reg15 reg14 reg13 reg12 reg11 0 0 0 write: reset:00000000 figure 5-2. register initialization register (initrg) operating modes and resource mapping mc68hc812a4 data sheet, rev. 7 60 freescale semiconductor 5.4.3 ram initialization register after reset, addresses of the 1-kbyte ram array begin at location $0800 but can be assigned to any 2-kbyte boundary within the standard 64-kbyte address sp ace. mapping of internal ram is controlled by five bits in the initrm register. the ram array occupies the last 1 kbyte of the 2-kbyte block. read: anytime write: once in normal modes; anytime in special modes ram15?ram11 ? ram position bits these bits specify the upper five bits of the 16-bit ram address. 5.4.4 eeprom initia lization register the mcu has 4 kbytes of eeprom which is acti vated by the eeon bit in the initee register. mapping of internal eeprom is cont rolled by four bits in the init ee register. after reset, eeprom address space begins at location $1000 but can be mapped to any 4-kbyte boundary within the standard 64-kbyte address space. read: anytime write: varies from bit to bit ee15?ee12 ? eeprom position bits these bits specify the upper four bits of the 16-bit eeprom address. normal modes: write once special modes: write anytime eeon ? eeprom on bit eeon enables the on-chip eeprom. eeon is forced to 1 in single-chip modes. write anytime 1 = eeprom at address selected by ee15?ee12 0 = eeprom removed from memory map address: $0010 bit 7654321bit 0 read: ram15 ram14 ram13 ram12 ram11 0 0 0 write: reset:00001000 figure 5-3. ram initialization register (initrm) address: $0012 bit 7654321bit 0 read: ee15 ee14 ee13 ee12 0 0 0 eeon write: reset: expanded and peripheral:00010001 single-chip:11110001 figure 5-4. eeprom initiali zation register (initee) mode and resource mapping registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 61 5.4.5 miscellaneous mapp ing control register additional mapping controls are av ailable that can be used in conjunction with memory expansion and chip selects. to use memory expansion, the part must be operated in one of the expanded modes. sections of the standard 64-kbyte memory map have memory expansion windows which allow more than 64 kbytes to be addressed externally. memory expansion consists of three memory expansion windows and six address lines in addition to the existing standard 16 address lines. the memory expansion function reuses as many as six of the standard 16 address lines . usage of chip selects identifies the source of the internal address. all of the memory expansion windows have a fixed si ze and two of them have a fixed address location. the third has two selectable address locations. read: anytime write: once in normal modes; anytime in special modes ewdir ? extra window positioned in direct space bit this bit is only valid in expanded modes. if the ewen bit in the windef register is cleared, then this bit has no meaning or effect. 1 = if ewen is set, then a 1 in this bit places the epage at $0000?$03ff. 0 = if ewen is set, then a 0 in this bit places the epage at $0400?$07ff. ndrc ? narrow data bus for register chip-select space bit this function requires at least one of the chip se lects cs3?cs0 to be enabled. it effects the external 512-byte memory space. 1 = makes the register-following chip-selects (2, 1, 0, and sometimes 3) active space (512-byte block) act the same as an 8-bit only external data bus. data only goes through port c externally. this allows 8-bit and 16-bit external memory devices to be mixed in a system. 0 = makes the register-following chip-select active space act as a full 16-bit data bus. in the narrow (8-bit) mode, ndrc has no effect. address: $0013 bit 7654321bit 0 read: ewdirndrc000000 write: reset:00000000 figure 5-5. miscellaneous mapping control register (misc) operating modes and resource mapping mc68hc812a4 data sheet, rev. 7 62 freescale semiconductor 5.5 memory map figure 5-6 illustrates the memory map for each m ode of operation immediately after reset. figure 5-6. memory map $1fff registers mappable to any 2-k space $01ff ram mappable to any 2-k space single-chip normal single-chip special ext ext $0bff $ffff $f000 eeprom mappable to any 4-k space $1000 ext vectors vectors bdm if active eeprom single-chip modes $ffff $0000 $0800 $ffff $ff00 $ff00 $f000 $1000 $0000 $0800 $2000 $ffc0 expanded vectors mc68hc812a4 data sheet, rev. 7 freescale semiconductor 63 chapter 6 bus control and input/output (i/o) 6.1 introduction internally the mcu has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be 8 or 16 bits. t here are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the lstrb signal to indicate 8-bit or 16-bit data. 6.2 detecting access type from external signals the external signals lstrb , r/w , and a0 can be used to determine the type of bus access that is taking place. accesses to the internal ram module are the only type of access that produce lstrb = a0 = 1, because the internal ram is specif ically designed to allow misaligned 16- bit accesses in a single cycle. in these cases, the data for the address that was accessed is on the low half of the data bus and the data for address +1 is on the high half of the data bus. 6.3 registers not all registers are visible in the memory map under certain conditions. in special peripheral mode, the first 16 registers associated with bus expansion are removed from the memory map. in expanded modes, some or all of port a, port b, port c, port d, and port e are used for expansion buses and control signals. to allow emulation of the single-c hip functions of these ports, some of these registers must be rebuilt in an external port replacement unit. in any expanded mode, port a, port b, and port c are used for address and data lines so registers for thes e ports, as well as the data direction registers for these ports, are removed from the on-chip memory map and become external accesses. table 6-1. access type versus bus control pins lstrb a0 r/w type of access 1 0 1 8-bit read of an even address 0 1 1 8-bit read of an odd address 1 0 0 8-bit write of an even address 0 1 0 8-bit write of an odd address 0 0 1 16-bit read of an even address 111 16-bit read of an odd address (low/high data swapped) 0 0 0 16-bit write to an even address 110 16-bit write to an even address (low/high data swapped) bus control and input/output (i/o) mc68hc812a4 data sheet, rev. 7 64 freescale semiconductor port d and its associated data direction register may be removed from the on-chip map when port d is needed for 16-bit data transfers. if the mcu is in an expanded wide mode, port c and port d are used for 16-bit data and the associated port and data direct ion registers become external accesses. when the mcu is in expanded narrow mode, the external data bu s is normally 8 bits. to allow full-speed operation while allowing visibility of internal 16-bit accesses , a 16-bit-wide data path is required. the emulate port d (emd) control bit in the mode register may be set to allow such 16-bit transfers. in this case of narrow special expanded mode and the emd bit set, port d and data direction d registers are removed from the on-chip memory map and become external access es so port d may be rebuilt externally. in any expanded mode, port e pins may be needed for bus control (for instance, eclk and r/w ). to regain the single-chip functions of port e, the emulat e port e (eme) control bit in the mode register may be set. in this special case of expanded mode and eme set, porte and ddre registers are removed from the on-chip memory map and become external accesses so port e may be rebuilt externally. 6.3.1 port a data register read: anytime, if register is in the map write: anytime, if register is in the map bits pa7?pa0 are associated with addresses addr15?a ddr8 respectively. when th is port is not used for external addresses such as in single-chip m ode, these pins can be used as general-purpose i/o. ddra determines the primary direction of each pin. th is register is not in the on-chip map in expanded and peripheral modes. 6.3.2 port a data direction register read: anytime, if register is in the map write: anytime, if register is in the map this register determines the primary direction for each port a pin when functioni ng as a general-purpose i/o port. ddra is not in the on-chip map in expanded and peripheral modes. 1 = associated pin is an output. 0 = associated pin is a high-impedance input. address: $0000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset:00000000 expanded and peripheral: addr15 addr 14 addr13 addr12 addr11 addr10 addr9 addr8 figure 6-1. port a data register (porta) address: $0002 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 6-2. port a data direction register (ddra) registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 65 6.3.3 port b data register read: anytime, if register is in the map write: anytime, if register is in the map bits pb7?pb0 correspond to address lines addr7?addr0. when this port is not used for external addresses such as in single-chip mode, thes e pins can be used as general-purpose i/o. ddrb determines the primary direction of each pin. this register is not in the on-chip map in expanded and peripheral modes. 6.3.4 port b data direction register read: anytime, if register is in the map write: anytime, if register is in the map this register determines the primary direction for each port b pin when functioni ng as a general-purpose i/o port. ddrb is not in the on-chip map in expanded and peripheral modes. 1 = associated pin is an output. 0 = associated pin is a high-impedance input. address: $0001 bit 7654321bit 0 read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset:00000000 expanded and peripheral: addr7 add r6 addr5 addr4 addr3 addr2 addr1 addr0 figure 6-3. port b data register (portb) address: $0003 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 6-4. port b data direction register (ddrb) bus control and input/output (i/o) mc68hc812a4 data sheet, rev. 7 66 freescale semiconductor 6.3.5 port c data register read: anytime, if register is in the map write: anytime, if register is in the map bits pc7?pc0 correspond to data lines data15?data8. when this port is not used for external data such as in single-chip mode, these pins can be used as general-purpose i/o. ddrc determines the primary direction for each pin. in narrow ex panded modes, data15?data8 and data7?data0 are multiplexed into the mcu through port c pins on successi ve cycles. this register is not in the on-chip map in expanded and peripheral modes. when the mcu is operating in special expanded narrow mode and port c and port d are being used for internal visibility, internal accesses produce fu ll 16-bit information with data15?data8 on port c and data7?data0 on port d. this allows the mcu to operate at full speed while making 16-bit access information available to external development equipm ent in a single cycle. in this narrow mode, normal 16-bit accesses to external memo ry get split into two successive 8-bit accesses on port c alone. 6.3.6 port c data direction register read: anytime, if register is in the map write: anytime, if register is in the map ddrc is not in the on-chip map in expanded and per ipheral modes. this register determines the primary direction for each port c pin when functioning as a general-purpose i/o port. 1 = associated pin is an output. 0 = associated pin is a high-impedance input. address: $0004 bit 7654321bit 0 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset:00000000 expanded wide and peripheral: data15 data1 4 data13 data12 data11 data10 data9 data8 expanded narrow: data15/7 data14/6 data13/5 data12/4 data11/3 data10/2 data9/1 data8/0 figure 6-5. port c data register (portc) address: $0006 bit 7654321bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 figure 6-6. port c data direction register (ddrc) registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 67 6.3.7 port d data register read: anytime, if register is in the map write: anytime, if register is in the map bits pd7?pd0 correspond to data lines data7?data0. when port d is not used for external data, such as in single-chip mode, these pins can be used as general-purpose i/o or key wakeup signals. ddrd determines the primary direction of each port d pin. in special expanded narrow mode, the external data bus is normally limited to eight bits on port c, but the emulate port d bit (emd) in the mode register can be set to allow port c and port d to be used together to provide single-cycle visibility of internal 16-bit accesses for de bugging purposes. if the mode is special narrow expanded and emd is set, port d is configured for data7?data0 of visible internal accesses and normal 16-bit external accesses are split into two adjacent 8-bit accesses through port c. this allows connection of a single 8-bit external program memory. this register is not in the on-chip map in wide expanded and peripheral modes. also, in special narrow expanded mode, the function of this port is determined by the emd control bit. if emd is set, this register is not in the on-chip map and port d is used for data7?data0 of visible internal accesses. if emd is clear, this port serves as general-purpose i/o or key wakeup signals. 6.3.8 port d data direction register read: anytime, if register is in the map write: anytime, if register is in the map when port d is operating as a general-purpose i/o port, this register determines the primary direction for each port d pin. 1 = associated pin is an output. 0 = associated pin is a high-impedance input. this register is not in the map in wide expanded and peripheral modes. also, in special narrow expanded mode, the function of this port is determined by the emd control bit. if emd is set, this register is not in the on-chip map and port d is used for data7?data0 of visible internal accesses. if emd is clear, this port serves as general-purpos e i/o or key wakeup signals. address: $0005 bit 7654321bit 0 read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write: reset:00000000 expanded wide and peripheral: data7 data6 data5 data4 data3 data2 data1 data0 alternate pin function:kwd7kwd6kwd5kwd4kwd3kwd2kwd1kwd0 figure 6-7. port d data register (portd) address: $0007 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 6-8. port d data direction register (ddrd) bus control and input/output (i/o) mc68hc812a4 data sheet, rev. 7 68 freescale semiconductor 6.3.9 port e data register read: anytime, if register is in the map write: anytime, if register is in the map this register is associated with external bus cont rol signals and interrupt inputs including auxiliary reset (arst), mode select (modb/ipipe1, moda/ipipe0), e-clock, size (lstrb ), read/write (r/w ), irq , and xirq . when the associated pin is not used for one of thes e specific functions, the pin can be used as general-purpose i/o. the port e assi gnment register (pear) selects th e function of each pin. ddre determines the primary direction of each port e pin when configured to be general-purpose i/o. some of these pins have software selectable pullups (lstrb , r/w , and xirq ). a single control bit enables the pullups for all these pins which are configured as inputs. irq always has a pullup. pe7 can be selected as a high-true auxiliary reset input. this register is not in the map in peripheral mode or expanded modes when the eme bit is set. 6.3.10 port e data direction register read: anytime, if register is in the map write: anytime, if register is in the map this register determines the primary direction for each port e pin configured as general-purpose i/o. 1 = associated pin is an output. 0 = associated pin is a high-impedance input. pe1 and pe0 are associated with xirq and irq and cannot be configured as outputs. these pins can be read regardless of whether the alternate interrupt functions are enabled. this register is not in the map in peripheral mode and expanded modes while the eme control bit is set. address: $0008 bit 7654321bit 0 read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset: unaffected by reset normal narrow expanded:00001000 all other modes:00000000 alternate pin function: arst modb or ipipe1 moda or ipipe0 eclk lstrb r/w irq xirq figure 6-9. port e data register (porte) address: $0009 bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000011 normal narrow expanded: 00001000 all other modes:00000000 figure 6-10. port e data direction register (ddre) registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 69 6.3.11 port e assignment register read: anytime, if register is in the map write: varies from bit to bit if register is in the map the pear register selects between the general-purpose i/o functions and the alternate bus-control functions of port e. the alternate bus-contro l functions override the associated ddre bits. the reset condition of this register depends on the mode of operation. in normal single-chip mode, port e is general-purpose i/o. in special single-chip mode, the e-clock is enabled as a timing reference, and the rest of port e is general-purpose i/o. in normal expanded modes, the e-clock is configur ed for its alternate bus-control function, and the other bits of port e are general-purpose i/o. the reset vector is located in external memory and the e-clock may be required for this access. if r/w is needed for external writable resources, pear can be written during normal expanded modes. in special expanded modes, ipipe1, ipipe0, e, r/w , and lstrb are configured as bus-control signals. in peripheral mode, the pear register is not accessib le for reads or writes. ho wever, the pllte control bit is cleared to configure pe6 as a test output from the pll module. arsie ? auxiliary reset input enable bit write anytime. 1 = pe7 is a high-true reset input; reset timi ng is the same as that of the low-true reset pin. 0 = pe7 is general-purpose i/o. pllte ? pll testing enable bit normal modes: write never special modes: write anytime except the first time 1 = pe6 is a test signal output from the pll m odule (no effect in single-chip or normal expanded modes); pipoe = 1 overrides this function and fo rces pe6 to be a pipe status output signal. 0 = pe6 is general-purpose i/o or pipe output. address: $000a bit 7654321bit 0 read: arsie pllte pipoe neclk lstre rdwe 0 0 write: reset: special single-chip:00101100 special expanded narrow:00101100 peripheral:01010000 special expanded wide:00101100 normal single-chip00010000 normal expanded narrow:00000000 normal expanded wide:00000000 figure 6-11. port e assignment register (pear) bus control and input/output (i/o) mc68hc812a4 data sheet, rev. 7 70 freescale semiconductor pipoe ? pipe status signal output enable bit normal modes: write once special modes: write anytime except the first time 1 = pe6 and pe5 are outputs and indicate the state of the instruction queue; no effect in single-chip modes. 0 = pe6 and pe5 are general-purpose i/o; if pllte = 1, pe6 is a test output signal from the pll module. neclk ? no external e clock bit normal modes: write anytime special modes: write never in peripheral mode, e is an input; in all other modes, e is an output. 1 = pe4 is a general-purpose i/o pin. 0 = pe4 is the external e-clock pin. to get a free-running e-clock in single-chip modes, use neclk = 0 and ivis = 1. a 16-bit write to pear:mode can configure these bits in one operation. lstre ? low strobe (lstrb ) enable bit normal modes: write once special modes: write anytime except the first time lstre has no effect in single-chip or normal expanded narrow modes. 1 = pe3 is configured as the lstrb bus-control output, except in single-chip or normal expanded narrow modes. 0 = pe3 is a general-purpose i/o pin. lstrb is for external writes. after reset in normal expanded mode, lstrb is disabled. if needed, it must be enabled before external writes. external reads do not normally need lstrb because all 16 data bits can be driven even if the mcu only needs eight bits of data. in normal expanded narrow mode, this pin is reset to an output driving high allowing the pin to be an output while in and immediately after reset. rdwe ? read/write enable bit normal modes: write once special modes: write anytime except the first time rdwe has no effect in single-chip modes. 1 = pe2 is configured as the r/w pin. in single-chip modes, rdw e has no effect and pe2 is a general-purpose i/o pin. 0 = pe2 is a general-purpose i/o pin. r/w is used for external writes. after reset in norma l expanded mode, it is disabled. if needed, it must be enabled before any external writes. registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 71 6.3.12 pullup control register read: anytime, if register is in the map write: anytime, if register is in the map this register is not in the map in peripheral mode. these bits select pullup resistors for any pin in the corresponding port that is currently configured as an input. puph ? pullup port h enable bit 1 = enable pullup devices for all port h input pins 0 = port h pullups disabled pupg ? pullup port g enable bit 1 = enable pullup devices for all port g input pins 0 = port g pullups disabled pupf ? pullup port f enable bit 1 = enable pullup devices for all port f input pins 0 = port f pullups disabled pupe ? pullup port e enable bit 1 = enable pullup devices for port e input pins pe3, pe2, and pe0 0 = port e pullups on pe3, pe2, and pe0 disabled pupd ? pullup port d enable bit 1 = enable pullup devices for all port d input pins 0 = port d pullups disabled this bit has no effect if port d is being used as part of the data bus (the pullups are inactive). pupc ? pullup port c enable bit 1 = enable pullup devices for all port c input pins 0 = port c pullups disabled this bit has no effect if port c is being used as part of the data bus (the pullups are inactive). pupb ? pullup port b enable bit 1 = enable pullup devices for all port b input pins 0 = port b pullups disabled this bit has no effect if port b is being used as part of the address bus (the pullups are inactive). pupa ? pullup port a enable bit 1 = enable pullup devices for all port a input pins 0 = port a pullups disabled this bit has no effect if port a is being used as part of the address bus (the pullups are inactive). address: $000c bit 7654321bit 0 read: puph pupg pupf pupe pupd puc pupb pupa write: reset:11111111 figure 6-12. pullup control register (pucr) bus control and input/output (i/o) mc68hc812a4 data sheet, rev. 7 72 freescale semiconductor 6.3.13 reduced drive register read: anytime, if register is in the map write: anytime, in normal modes; never in special modes this register is not in the map in peripheral mode. these bits select reduced drive for the associated port pins. this gives reduced power consumption and reduced rfi with a slight increase in transition ti me (depending on loading). the reduced drive function is independent of which function is being used on a particular port. rdpj ? reduced drive of port j bit 1 = reduced drive for all port j output pins 0 = full drive for all port j output pins rdph ? reduced drive of port h bit 1 = reduced drive for all port h output pins 0 = full drive for all port h output pins rdpg ? reduced drive of port g bit 1 = reduced drive for all port g output pins 0 = full drive for all port g output pins rdpf ? reduced drive of port f bit 1 = reduced drive for all port f output pins 0 = full drive for all port f output pins rdpe ? reduced drive of port e bit 1 = reduced drive for all port e output pins 0 = full drive for all port e output pins rdpd ? reduced drive of port d bit 1 = reduced drive for all port d output pins 0 = full drive for all port d output pins rdpc ? reduced drive of port c bit 1 = reduced drive for all port c output pins 0 = full drive for all port c output pins rdpab ? reduced drive of port a and port b bit 1 = reduced drive for all port a and port b output pins 0 = full drive for all port a and port b output pins address: $000d bit 7654321bit 0 read: rdpj rdph rdpg rdpf rdpe prpd rdpc rdpab write: reset:00000000 figure 6-13. reduced drive register (rdriv) mc68hc812a4 data sheet, rev. 7 freescale semiconductor 73 chapter 7 eeprom 7.1 introduction the mc68hc812a4 eeprom (electrically erasable, programmable, read-only memory) serves as a 4096-byte nonvolatile memory which can be used for fr equently accessed static data or as fast access program code. operating system kernels and standar d subroutines would benefit from this feature. the mc68hc812a4 eeprom is arranged in a 16-bit c onfiguration. the eeprom array may be read as either bytes, aligned words, or misaligned words. access times are one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. programming is by byte or aligned word. attempts to program or erase misaligned words will fail. only the lower byte will be latched and programmed or erased. programmin g and erasing of the user eeprom can be done in all modes. each eeprom byte or aligned word must be er ased before programming. the eeprom module supports byte, aligned word, row (32 bytes), or bulk erase, all using the internal charge pump. bulk erasure of odd and even rows is also possible in test modes; the erased state is $ff. the eeprom module has hardware interlocks which protect stored data from corruption by accidentally enabling the program/erase voltage. programming voltage is derived from the internal v dd supply with an internal charge pump. the eeprom has a minimum program/erase life of 10,000 cycles over the complete operating temperature range. 7.2 eeprom programmer?s model the eeprom module consists of tw o separately addressable sections. the first is a 4-byte memory mapped control register block used for control, testing and configuration of the eeprom array. the second section is the eeprom array itself. at reset, the 4-byte register section starts at address $00f0 and the eeprom array is located from addresses $1000 to $1fff (see figure 7-1 ). for information on remapping the register block and eeprom address space, refer to chapter 5 operating modes and resource mapping . read/write access to the memory array section c an be enabled or disabled by the eeon control bit in the initee register. this feature allows the access of me mory mapped resources that have lower priority than the eeprom memory array. eeprom control regist ers can be accessed an d eeprom locations may be programmed or erased regardless of the state of eeon. using the normal eeprog control, it is possible to continue program/e rase operations during wait. for lowest power consumption during wait, stop program/erase by turning off eepgm. if the stop mode is entered during programming or eras ing, program/erase voltage is automatically turned off and the rc clock (if enabled) is stopped. however, the eepgm control bit remains set. when stop mode is terminated, the progra m/erase voltage automatically tu rns back on if eepgm is set. at low bus frequencies, the rc clock must be turned on for program/erase. eeprom mc68hc812a4 data sheet, rev. 7 74 freescale semiconductor figure 7-1. eeprom block protect mapping 7.3 eeprom control registers this section describes the eeprom control registers. 7.3.1 eeprom module c onfiguration register read: anytime write: varies from bit to bit eeswai ? eeprom stops in wait mode bit 0 = module is not affected during wait mode. 1 = module ceases to be clocked during wait mode. this bit should be cleared if the wait mode vectors are mapped in the eeprom array. protlck ? block protect write lock bit 0 = block protect bits and bulk erase protection bit can be written. 1 = block protect bits are locked. write once in normal modes (smodn = 1). set and clear anytime in specia l modes (smodn = 0). eerc ? eeprom charge pump clock bit 0 = system clock is used as clock source for the internal charge pump; internal rc oscillator is stopped. 1 = internal rc oscillator drives the charge pump; rc oscillator is required when the system bus clock is lower than f prog . write: anytime address: $00f0 bit 7654321bit 0 read: 11111 eeswai protlck eerc write: reset:11111100 figure 7-2. eeprom module configuration register (eemcr) bprot0 64 bytes bprot6 bprot5 bprot4 bprot3 bprot2 bprot1 $_000 $_800 $_c00 $_e00 $_f00 $_f80 $_fc0 $_fff 2 kbytes 1 kbyte 512 bytes 256 bytes 128 bytes 64 bytes reserved 64 bytes vectors 64 bytes single-chip vectors $ff80 $ffbf $ffc0 $ffff eeprom control registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 75 7.3.2 eeprom bloc k protect register read: anytime write: anytime if eepgm = 0 and protlck = 0 this register prevents acci dental writes to eeprom. bprot6?bprot0 ? eeprom block protection bit 0 = associated eeprom block c an be programmed and erased. 1 = associated eeprom block is protec ted from being pr ogrammed and erased. these bits cannot be modified while pr ogramming is taking place (eepgm = 1). 7.3.3 eeprom test register read: anytime write: in special modes only (smodn = 0) these bits are used for test purposes only. in normal modes, the bits are forced to 0. eeodd ? odd row programming bit 1 = bulk program/erase all odd rows 0 = odd row bulk programming/erasing disabled address: $00f1 bit 7654321bit 0 read: 1 bprot6 bprot5 bprot4 bprot3 bprot2 bprot1 bprot0 write: reset:11111111 figure 7-3. eeprom block protect register (eeprot) table 7-1. 4-kbyte eeprom block protection bit name block protected block size bprot6 $1000 to $17ff 2048 bytes bprot5 $1800 to $1bff 1024 bytes bprot4 $1c00 to $1dff 512 bytes bprot3 $1e00 to $1eff 256 bytes bprot2 $1f00 to $1f7f 128 bytes bprot1 $1f80 to $1fbf 64 bytes bprot0 $1fc0 to $1fff 64 bytes address: $00f2 bit 7654321bit 0 read: eeodd eeven marg eecpd eecprd 0 eecpm 0 write: reset:00000000 = unimplemented figure 7-4. eeprom test register (eeprot) eeprom mc68hc812a4 data sheet, rev. 7 76 freescale semiconductor eeven ? even row programming bit 1 = bulk program/erase all even rows 0 = even row bulk programming/erasing disabled marg ? program and erase voltage margin test enable bit 1 = program and erase margin test 0 = normal operation this bit is used to evaluate the program/erase voltage margin. eecpd ? charge pump disable bit 1 = disable charge pump 0 = charge pump is turned on during program/erase eecprd ? charge pump ramp disable bit 1 = disable charge pump controlled ramp up 0 = charge pump is turned on progressively during program/erase this bit is known to enhance write/erase endurance of eeprom cells. ecpm ? charge pump monitor enable bit 1 = output the charge pump voltage on the irq /v pp pin 0 = normal operation 7.3.4 eeprom programming register read: anytime write: varies from bit to bit bulkp ? bulk erase protection bit 1 = eeprom protected from bulk or row erase 0 = eeprom can be bulk erased. write anytime, if eepgm = 0 and protlck = 0 byte ? byte and aligned word erase bit 1 = one byte or one aligned word erase only 0 = bulk or row erase enabled write anytime, if eepgm = 0 row ? row or bulk erase bit (when byte = 0) 1 = erase only one 32-byte row 0 = erase entire eeprom array write anytime, if eepgm = 0 byte and row have no effect when erase = 0. if byte = 1 and test mode is not enabled, only the lo cation specified by the address written to the programming latches is erased. the operation is a byte or an aligned word erase depending on the size of written data. address: $00f3 bit 7654321bit 0 read: bulkp 0 0 byte row erase eelat eepgm write: reset:10000000 figure 7-5. eeprom programming register (eeprog) eeprom control registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 77 erase ? erase control bit 1 = eeprom configuration for erasure 0 = eeprom configuration for programming write anytime, if eepgm = 0 this bit configures the eeprom for erasure or programming. eelat ? eeprom latch control bit 1 = eeprom address and data bus latches set up for programming or erasing 0 = eeprom set up for normal reads write: anytime, if eepgm = 0 note when eelat is set, the entire eeprom is unavailable for reads; therefore, no program residing in the eeprom can be executed while attempting to program unused eeprom space. care sh ould be taken that no references to the eeprom are used while programming. interrupts should be turned off if the vectors are in the eeprom. timing and any serial communications must be done with polling during the programming process. byte, row, erase, and eelat bits can be wr itten simultaneously or in any sequence. eepgm ? program and erase enable bit 1 = applies program/erase voltage to eeprom 0 = disables program/erase voltage to eeprom the eepgm bit can be set only after eelat has been set. when eelat and eepgm are set simultaneously, eepgm remains clear but eelat is set. the bulkp, byte, row, erase, and eelat bits cannot be changed when eepgm is set. to complete a program or erase, two successive writes to clear eepgm and eelat bits are required before reading the programmed data. a write to an eeprom location has no effect when eepgm is set. latched address and data cannot be modified during program or erase. a program or erase operation should follow this sequence: 1. write byte, row, and erase to the desired value; write eelat = 1. 2. write a byte or an aligned word to an eeprom address. 3. write eepgm = 1. 4. wait for programming ( t prog ) or erase ( t erase ) delay time. 5. write eepgm = 0. 6. write eelat = 0. by jumping from step 5 to step 2, it is possible to program/erase more bytes or words without intermediate eeprom reads. table 7-2. erase selection byte row block size 0 0 bulk erase entire eeprom array 0 1 row erase 32 bytes 1 0 byte or aligned word erase 1 1 byte or aligned word erase eeprom mc68hc812a4 data sheet, rev. 7 78 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 79 chapter 8 memory expansion and chip-select 8.1 introduction to use memory expansion, the mcu must be operated in one of the expanded modes. sections of the standard 64-kbyte address space have memory expansion windows which allow an external address space larger than 64 kbytes. memory expansion cons ists of three memory expansion windows and six address lines which are used in addition to the standard 16 address lines. the memory expansion function reuses as many as six of the standard 16 address lines. to do this, some of the upper address lines of internal addresses falli ng in an active window are overridden. consequently, the address viewed externally may not match the in ternal address. usage of ch ip-selects identify the source of the internal address for debugging and selection of the proper external devices. all memory expansion windows have a fixed size and two have a fixed address location. the third has two selectable address locations. when an internal a ddress falls into one of these active windows, it is translated as shown in table 8-1 . addresses addr9?addr0 are not affected by memory expansion and are the same externally as they are internally. addresses addr21?addr16 are g enerated only by memory expansion and are individually enabled by software-programmable co ntrol bits. if not enabled, they may be used as general-purpose i/o (input/output). addresses addr 15?addr10 can be the internal addresses or they can be modified by the memory expansion module. these are not avai lable as general-purpose i/o in expanded modes. table 8-1. memory expansion values (1) internal address a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 $0000?$03ff ewdir (2) = 1, ewen = 1 1 1 1 1 pea17 pea16 pea15 pea14 pea13 pea12 pea11 pea10 $0000?$03ff ewdir or ewen = 0 111111a15a14a13a12a11a10 $0400?$07ff ewdir = 0, ewen = 1 1 1 1 1 pea17 pea16 pea15 pea14 pea13 pea12 pea11 pea10 $0400?$07ff ewdir = 1, ewen = x or ewdir = x, ewen = 0 111111a15a14a13a12a11a10 memory expansion and chip-select mc68hc812a4 data sheet, rev. 7 80 freescale semiconductor 8.2 generation of chip-selects to use chip-selects the mcu must be in one of the expanded modes. each of the seven chip-selects has an address space for which it is active ? that is, w hen the current cpu address is in the range of that chip-select, it becomes active. chip-selects are gener ally used to reduce or eliminate external address decode logic. these active low signals usually are conn ected directly to the chip-select pin of an external device. 8.2.1 chip-selects in dependent of me mory expansion three types of chip-selects are program memory chip-selects, other memory chip-selects and peripheral chip-selects. memory chip-selects cover a medium -to-large address space. peripheral chip-selects (cs3?cs0) cover a small address space. the program memory chip-select includes the vector space and is generally used with non-volatile memory. to star t the user?s program, the program chip-select is designed to be active out of reset. this is the only chip-select which has a func tional difference from the others, so a small memory could use a peripheral chip-select and a peripheral could use a memory chip-select. figure 8-1 shows peripheral chip-selects in an expanded portion of the memory map. table 8-2 shows the register settings that correspond to the example. chip-selects cs2?cs0 always map to the same 2-kbyte block as the internal register space. the internal registers cover the first 512 bytes and these chip-selects cover all or part of the 512 bytes follow ing the register space blocking out a full 1-kbyte space. cs3 can map with these other chip-selects or be used in a 1-kbyte space by itself which starts at either $0000 or $0400. cs3 can be used only for a 1-kb yte space when it selects the e page of memory expansion and e page is active. $0800?$6fff 1 1 1111a15a14a13a12a11a10 $7000?$7fff dwen = 1 1 1 pda19 pda18 pda17 pda16 pda15 pda14 pda13 pda12 a11 a10 $7000?$7fff dwen = 0 111111a15a14a13a12a11a10 $8000?$bfff pwen = 1 ppa21 ppa20 ppa19 ppa18 ppa17 ppa16 ppa15 ppa14 a13 a12 a11 a10 $8000?$bfff pwen = 0 111111a15a14a13a12a11a10 $c000?$ffff 1 1 1111a15a14a13a12a11a10 1. all port g assigned to memory expansion 2. the ewdir bit in the misc register selects the e window address (1 = $0000?$03ff including direct space and 0 = $0400?$07ff). table 8-1. memory expansion values (1) (continued) internal address a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 generation of chip-selects mc68hc812a4 data sheet, rev. 7 freescale semiconductor 81 cs3 can be used with a 1-kbyte s pace in systems not using memory expansion. however, it must be made to appear as if memory expansion is in us e. one of many possible configurations is: select the desired 1-kbyte space for epage (ewdir in misc in the mmi). write the epage register with $0000, if ewdir is one or $0001 if ewdir is 0. designate all port g pins as i/o. enable epage and cs3. make cs3 follow epage. 8.2.2 chip-selects used in conjunction with memory expansion memory expansion and chip-select functions can wo rk independently, but syst ems requiring memory expansion perform better when chip-selects are also used. for each memory expansion window there is a chip-select (or two) designed to function with it. figure 8-2 shows a memory expansion and chip-selec t example using three chip-selects. table 8-3 shows the register settings that co rrespond to the example. the program space consists of 128 kbytes of addressable memory in eight 16-kbyte pages. page 7 is always accessible in the space from $c000 to $ffff. the data space consists of 64 kbytes of addressable memory in 16, 4-kbyte pages. unless csd is used to select the external ram, pages 0 through 6 appear in the $0000 to $6fff space wherever there is no higher priority resource . the extra space consists of four , 1-kbyte pages making 4 kbytes of addressable memory. if memory is increased to the maximum in this exampl e, the program space will consist of 4 mbytes of addressable space with 256 16-kbyte pages and page $ ff always available. the data space will be 1 mbyte of addressable space with 256 4-kbyte pages and pages $f0 to $f6 mirrored to the $0000 to $6fff space. the extra space will be 256 kbytes of addressable space in 256 1-kbyte pages. memory expansion and chip-select mc68hc812a4 data sheet, rev. 7 82 freescale semiconductor figure 8-1. chip-selects cs3?cs0 partial memory map table 8-2. example register settings register value meaning initrm $00 assigns internal ram to $0000?$0fff initrg $08 assigns register block to $0800?$09ff and register-following chip-selects at $0a00?$0bff windef $20 enable epage mxar $00 no port g lines assigned as extended address csctl0 $xf enables cs3, cs2, cs1, and cs0 csctl1 $x8 makes cs3 follow epage misc %0xxxxxxx puts epage at $0400?$07ff epage $01 keeps the translated value of the upper addresses the same as it would have been before translation; not necessary if all external devices use chip-selects $0000 $0100 $0200 $0300 $0400 $0500 $0600 $0700 $0800 $0900 $0a00 $0b00 $0c00 $0d00 $0e00 $0f00 $0fff internal space ram 1 kbyte registers external space cs0 cs1 256 bytes 128 bytes 128 bytes 1 kbyte cs3 cs2 generation of chip-selects mc68hc812a4 data sheet, rev. 7 freescale semiconductor 83 figure 8-2. memory expansion and chip-select example table 8-3. example register settings register value meaning windef $e0 enable epage, dpage, ppage mxar $01 port g bit 0 assigned as extended address addr16 csctl0 %00111xxx enables csp0, csd, and cs3 csctl1 $18 makes csd follow $0000?$7fff and cs3 select epage misc %0xxxxxxx puts epage at $0400?$09ff $0000 $1000 $2000 $3000 $4000 $5000 $6000 $7000 $8000 $9000 $a000 $b000 $c000 $d000 $e000 $f000 $ffff $ffc0?$ffff 0 1 2 3 4 5 6 page 7 data chip-select: (csd) $0000 to $7fff data window: $7000 to $7fff program chip-select 0: (csp0) $8000 to $ffff program pages: $8000 to $bfff 0 1 2 page 3 chip-select 3: (cs3) $0400 to $07ff external space internal space registers & ram & cs[3:0] eeprom vectors note 2 x4 x5 x6 x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xa xb xc xd xe page xf note 1: some 4-kbyte blocks of phys- ical external data memory can be se- lected by an access to $0000?$6fff in the 64-kbyte map or as pages 0 through 6 in the data window. on-chip registers, eeprom, and epage have higher priority than csd. note 2: the last page of physical pro- gram memory can be selected by an access to $c000?$ffff in the 64-kbyte map or as page 7 in the pro- gram window. note 1 . . . memory expansion and chip-select mc68hc812a4 data sheet, rev. 7 84 freescale semiconductor 8.3 chip-select stretch each chip-select can be chosen to stretch bus cycles as sociated with it. stretch can be zero, one, two, or three whole cycles added which allows interfacing to external devices which cannot meet full bus speed timing. figure 8-3 , figure 8-4 , figure 8-5 , and figure 8-6 show the waveforms for zero to three cycles of stretch. figure 8-3. chip-select with no stretch figure 8-4. chip-select with 1-cycle stretch figure 8-5. chip-select with 2-cycle stretch figure 8-6. chip-select with 3-cycle stretch unstretched bus cycle cs internal e-clock eclk pin cs stretched internal e-clock eclk pin stretched by 1 cycle cs stretched internal stretched by 2 cycles e-clock eclk pin stretched by 3 cycles cs stretched internal e-clock eclk pin memory expansion registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 85 the external e-clock may be the stretched e-clock, the e-clock, or no clock depending on the selection of control bits estr and ivis in the mode register and neclk in the pear register. 8.4 memory expansion registers this section describes the memory expansion registers. 8.4.1 port f data register read: anytime write: anytime seven port f pins are associated wi th chip-selects. any pin not used as a chip-select can be used as general-purpose i/o. all pins are pulled up when inpu ts (if pullups are enabled) . enabling a chip-select overrides the associated data direction bit and port data bit. 8.4.2 port g data register read: anytime write: anytime six port g pins are associated with memory expansio n. any pin not used for memory expansion can be used as general-purpose i/o. all pins are pulled up w hen inputs (if pullups are enabled). enabling a memory expansion address with the memory expansion assignment register overrides the associated data direction bit and port data bit. address: $0030 bit 7654321bit 0 read: 0 pf6 pf5 pf4 pf3 pf2 pf1 pf0 write: reset:00000000 = unimplemented alternate pin function: csp1 csp0 csd cs3 cs2 cs1 cs0 figure 8-7. port f data register (portf) address: $0031 bit 7654321bit 0 read: 0 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented alternate pin function: addr2 1 addr20 addr19 addr18 addr17 addr16 figure 8-8. port g data register (portg) memory expansion and chip-select mc68hc812a4 data sheet, rev. 7 86 freescale semiconductor 8.4.3 port f data direction register read: anytime write: anytime when port f is active, ddrf determines pin direction. 1 = associated bit is an output. 0 = associated bit is an input. 8.4.4 port g data direction register read: anytime write: anytime when port g is active, ddrg determines pin direction. 1 = associated bit is an output. 0 = associated bit is an input. 8.4.5 data page register read: anytime write: anytime when enabled (dwen = 1), the value in this register determines which of the 256 4-kbyte pages is active in the data window. an access to the data page memory area ($7000 to $7fff) forces the contents of dpage to address pins addr15?addr12 and exp ansion address pins addr19?addr16. bits addr20 and addr21 are forced to 1 if enabled by mxar. data chip-select (csd) must be used in conjunction with this memory expansion window. address: $0032 bit 7654321bit 0 read: 0 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 = unimplemented figure 8-9. port f data direction register (ddrf) address: $0033 bit 7654321bit 0 read: 0 0 ddrg5 ddrg4 ddrg3 ddrg2 ddrg1 ddrg0 write: reset:00000000 = unimplemented figure 8-10. port g data direction register (ddrg) address: $0034 bit 7654321bit 0 read: pd19 pd18 pd17 pd16 pd15 pd14 pd13 pd12 write: reset:00000000 figure 8-11. data page register (dpage) memory expansion registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 87 8.4.6 program page register read: anytime write: anytime when enabled (pwen = 1), the value in this regist er determines which of the 256 16-kbyte pages is active in the program window. an access to the pr ogram page memory area ($8000 to $bfff) forces the contents of ppage to address pins addr15?addr14 and expansion address pins addr21?addr16. at least one of the program chip-selects (csp0 or csp1) must be used in conjunction with this memory expansion window. this register is used by the call an d rtc instructions to facilitate automatic program flow changing between pages of program memory. 8.4.7 extra page register read: anytime write: anytime when enabled (ewen = 1), the value in this register de termines which of the 256 1-kbyte pages is active in the extra window. an access to the extra page memory area forces the contents of epage to address pins addr15?addr10 and expans ion address pins addr1 6?addr17. address bits addr21?addr18 are forced to one (if enabled by mxar). chip-select 3 set to follow the extra page window (cs3 with cs3ep = 1) must be used in conjunction with this memory expansion window. 8.4.8 window definition register read: anytime write: anytime dwen ? data window enable bit 1 = enables paging of the data space (4 kbytes: $7000?$7fff) via the dpage register 0 = disables dpage address: $0035 bit 7654321bit 0 read: ppa21 ppa20 ppa19 ppa18 ppa17 ppa16 ppa15 ppa14 write: reset:00000000 figure 8-12. program page register (ppage) address: $0036 bit 7654321bit 0 read: pea17 pea16 pea15 pea14 pea13 pea12 pea11 pea10 write: reset:00000000 figure 8-13. extra page register (epage) address: $0037 bit 7654321bit 0 read: dwenpwenewen00000 write: reset:00000000 figure 8-14. window definition register (windef) memory expansion and chip-select mc68hc812a4 data sheet, rev. 7 88 freescale semiconductor pwen ? program window enable bit 1 = enables paging of the program space (16 kbytes: $8000?$bfff) via the ppage register 0 = disables ppage ewen ? extra window enable bit 1 = enables paging of the extra space (1 kbyte) via the epage register 0 = disables epage 8.4.9 memory expansion assignment register read: anytime write: anytime a21e, a20e, a19e, a18e, a17e, and a16e ? these bits select the memory expansion pins addr21?addr16. 1 = selects memory expansion for the associated bit function, overrides ddrg 0 = selects general-purpose i/o fo r the associated bit function in single-chip modes, these bits have no effect. 8.5 chip-selects the chip-selects are all active low. all pins in the associated port are pulled up when they are inputs and the pupf bit in pucr is set. if memory expansion is used, usually chip-selects should be used as well, since some translated addresses can be confused with untranslated add resses that are not in an expansion window. in single-chip modes, enabling the chip-select function does not affect the associated pins. the block of register-following chip-selects cs3?cs0 allows many combinations including: 512-byte cs0 256-byte cs0 and 256-byte cs1 256-byte cs0, 128-byte cs1, and 128-byte cs2 128-byte cs0, 128-byte cs1, 128-byte cs2, and 128-byte cs3 these register-following chip-selects are available in the 512-byte space next to and higher in address than the 512-byte space which includes the registers. for example, if the registers are located at $0800 to $09ff, then these register-following chip-selects are available in the space from $0a00 to $0bff. address: $0038 bit 7654321bit 0 read: 0 0 a21e a20e a19e a18e a17e a16e write: reset:00000000 = unimplemented figure 8-15. memory expansion assignment register (mxar) chip-select registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 89 8.6 chip-select registers this section describes the chip-select registers. 8.6.1 chip-select control register 0 read: anytime write: anytime bits have no effect on the associated pin in single-chip modes. csp1e ? chip-select program 1 enable bit this bit effectively selects the holes in the memory map. it can be used in conjunction with csp0 to select between two 2-mbyte devices based on address addr21. 1 = enables this chip-select which covers the space $8000 to $ffff or full map $0000 to $ffff 0 = disables this chip-select csp0e ? chip-select program 0 enable bit 1 = enables this chip-select which covers the program space $8000 to $ffff 0 = disables this chip-select csde ? chip-select data enable bit 1 = enables this chip-select which covers either $0000 to $7fff (csdhf = 1) or $7000 to $7fff (csdhf = 0) 0 = disables this chip-select cs3e ? chip-select 3 enable bit 1 = enables this chip-select which covers a 128-byte space followi ng the register space ($x280?$x2ff or $xa80?$xaff) alternately, it can be active for accesses within the extra page window. 0 = disables this chip-select cs2e ? chip-select 2 enable bit 1 = enables this chip-select which covers a 128-byte space followi ng the register space ($x380?$x3ff or $xb80?$xbff) 0 = disables this chip-select cs1e ? chip-select 1 enable bit cs2 and cs3 have a higher precedence and can ov erride cs1 for a portion of this space. 1 = enables this chip-select which covers a 256-byte space followi ng the register space ($x300?$x3ff or $xb00?$xbff) 0 = disables this chip-select address: $003c bit 7654321bit 0 read: 0 csp1e csp0e csde cs3e cs2e cs1e cs0e write: reset:00100000 = unimplemented figure 8-16. chip-select control register 0 (csctl0) memory expansion and chip-select mc68hc812a4 data sheet, rev. 7 90 freescale semiconductor cs0e ? chip-select 0 enable bit cs1, cs2, and cs3 have higher precedence and can override cs0 for portions of this space. 1 = enables this chip-select which covers a 512-byte space followi ng the register space ($x200?$x3ff or $xa00?$xbff) 0 = disables this chip-select 8.6.2 chip-select control register 1 read: anytime write: anytime csp1fl ? program chip-select 1 covers full map 1 = if cspa21 is cleared, chip-select program 1 covers the entire memory map. if cspa21 is set, this bit has no meaning or effect. 0 = if cspa21 is cleared, chip-select program 1 covers half the map, $8000 to $ffff. if cspa21 is set, this bit has no meaning or effect. cspa21 ? program chip-select split based on addr21 setting this bit allows two 2-mbyte memories to make up the 4-mbyte addressable program space. since addr21 is always one in the unpaged $c000 to $ffff space, csp0 is active in this space. 1 = program chip-selects are both active (if enabled) for space $8000 to $ffff; csp0 if addr21 is set and csp1 if addr21 is cleared. 0 = csp0 and csp1 do not rely on addr21. csdhf ? data chip-select covers half the map 1 = data chip-select covers half the memory map ($0000 to $7fff) including the optional data page window ($7000 to $7fff). 0 = data chip-select covers only $70 00 to $7fff (the optional data page window). cs3ep ? chip-select 3 follows extra page 1 = chip-select 3 follows accesses to the 1-kbyte extra page ($0400 to $07ff or $0000 to $03ff). any accesses to this window cause the chip-s elect to go active. (ewen must be set to 1.) 0 = chip-select 3 includes only accesses to a 128-byte space following the register space. address: $003d bit 7654321bit 0 read: 0 csp1fl cspa21 csdhf cs3ep 000 write: reset:00000000 = unimplemented figure 8-17. chip-select control register 1 (csctl1) chip-select registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 91 8.6.3 chip-select stretch registers each of the seven chip-selects has a 2-bit field in this register which determines the amount of clock stretch for accesses in that chip-select space. read: anytime write: anytime address: $003e bit 7654321bit 0 read: 0 0 srp1a srp1b srp0a srp0b strda strdb write: reset:00111111 = unimplemented figure 8-18. chip-select stretch register 0 (csstr0) address: $003f bit 7654321bit 0 read: str3a str3b str2a str2b str1a str1b str0a str0b write: reset:00111111 figure 8-19. chip-select stretch register 1 (csstr1) table 8-4. stretch bit definition stretch bit sxxxa stretch bit sxxxb number of e-clocks stretched 00 0 01 1 10 2 11 3 memory expansion and chip-select mc68hc812a4 data sheet, rev. 7 92 freescale semiconductor 8.7 priority only one module or chip-select may be selected at a time. if more than one modul e shares a space, only the highest priority module is selected. only one chip-select is active at any address. in th e event that two or more chip-selects cover the same address, only the highest priority chip-select is active. chip-selects have this order of priority: table 8-5. module priorities priority module or space highest on-chip register space ? 512 bytes fully blocked for registers although some of this space is unused bdm space (internal) ? when bdm is acti ve, this 256-byte block of registers and rom appear at $ffxx; cann ot overlap ram or registers on-chip ram on-chip eeprom (if enabled, eeon = 1) e space (external) (1) ? 1 kbyte at either $0000 to $03ff or $0400 to $07ff; may be used with ?extra? memory expansion and cs3 1. external spaces can be accessed only if the mcu is in expanded mode. priorities of differ- ent external spaces affect chip-selects and memory expansion. cs space (external) (1) ? 512 bytes following the 512-byte register space; may be used with cs3?cs0 p space (external) (1) ? 16 kbytes fixed at $8000 to $bfff; may be used with program memory expansion and csp0 and/or csp1 d space (external) (1) ? 4 kbytes fixed at $7000 to $7fff; may be used with data memory expansion and csd or csp1 (if set for full memory space) or the entire half of memory space $0000?$7fff lowest remaining external (1) highest lowest cs3 cs2 cs1 cs0 csp0 csd csp1 mc68hc812a4 data sheet, rev. 7 freescale semiconductor 93 chapter 9 key wakeups 9.1 introduction the key wakeup feature of the mc68hc812a4 issues an interrupt that wakes up the cpu when it is in stop or wait mode. three ports are associated with t he key wakeup function: port d, port h, and port j. port d and port h wakeups are triggered with a falli ng signal edge. port j key wakeups have a selectable falling or rising signal edge as th e active edge. for each pin which has an interrupt enabled, there is a path to the interrupt request signal which has no cloc ked devices when the part is in stop mode. this allows an active edge to bring the part out of stop. default register addresses, as established after rese t, are indicated in the following descriptions. for information on remapping the register block, refer to chapter 5 operating modes and resource mapping . 9.2 key wakeup registers this section provides a summary of the key wakeup registers. 9.2.1 port d data register this register is not in the map in wide expanded m odes or in special expanded narrow mode with mode register bit emd set. an interrupt is generated when a bit in the kwifd r egister and its corresponding kwied bit are both set. these bits correspond to the pins of port d. all ei ght bits/pins share the same interrupt vector and can wake the cpu when it is in stop or wait mode. ke y wakeups can be used with the pins configured as inputs or outputs. key wakeup port d shares a vector and control bit with irq . irqen must be set for key wakeup interrupts to signal the cpu. address: $0005 bit 7654321bit 0 read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write: reset:00000000 alternate pin function:kwd7kwd6kwd5kwd4kwd3kwd2kwd1kwd0 figure 9-1. port d data register (portd) key wakeups mc68hc812a4 data sheet, rev. 7 94 freescale semiconductor 9.2.2 port d data direction register read: anytime write: anytime this register is not in the map in wide expanded m odes or in special expanded narrow mode with mode register bit emd set. data direction register d is associated with port d and designates each pin as an input or output. ddrd7?ddrd0 ? data direction port d bits 1 = associated pin is an output. 0 = associated pin is an input. 9.2.3 port d key wakeup interrupt enable register read: anytime write: anytime this register is not in the map in wide expanded modes and in special expanded narrow mode with mode register bit emd set. kwied7?kwied0 ? key wakeup port d interrupt enable bits 1 = interrupt for the associated bit is enabled. 0 = interrupt for the associated bit is disabled. address: $0007 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 9-2. port d data direction register (ddrd) address: $0020 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 9-3. port d key wakeup interrupt enable register (kwied) key wakeup registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 95 9.2.4 port d key wakeup flag register read: anytime write: anytime each flag is set by a falling edge on its associated inpu t pin. to clear the flag, write 1 to the corresponding bit in kwifd. this register is not in the map in wide expanded m odes or in special expanded narrow mode with mode register bit emd set. kwifd7?kwifd0 ? key wakeup port d flags 1 = falling edge on the associated bit has occurred. an interrupt occurs if the associated enable bit is set. 0 = falling edge on the associated bit has not occurred. 9.2.5 port h data register read: anytime write: anytime port h is associated with key wakeup h. key wakeups can be used with the pins designated as inputs or outputs. ddrh determines whether each pin is an input or output. address: $0021 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 9-4. port d key wakeup flag register (kwifd) address: $0024 bit 7654321bit 0 read: ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 write: reset:00000000 alternate pin function:kwh7kwh6kwh5kwh4kwh3kwh2kwh1kwh0 figure 9-5. port h data register (porth) key wakeups mc68hc812a4 data sheet, rev. 7 96 freescale semiconductor 9.2.6 port h data direction register read: anytime write: anytime data direction register h is associated with port h and designates each pin as an input or output. ddrh7?ddrh0 ? data direction port h bits 1 = associated pin is an output. 0 = associated pin is an input. 9.2.7 port h key wakeup interrupt enable register an interrupt is generated when a bit in the kwifh r egister and its corresponding kwieh bit are both set. these bits correspond to the pins of port h. kwieh7?kwieh0 ? key wakeup port h interrupt enable bits 1 = interrupt for the associated bit is enabled. 0 = interrupt for the associated bit is disabled. 9.2.8 port h key wakeup flag register read: anytime write: anytime each flag is set by a falling edge on its associated input pin. to clear the flag, write one to the corresponding bit in kwifh. kwifh7?kwifh0 ? key wakeup port h flags 1 = falling edge on the associated bit has occurred (a n interrupt occurs if the associated enable bit is set) 0 = falling edge on the associated bit has not occurred address: $0025 bit 7654321bit 0 read: ddrh7 ddrh6 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 write: reset:00000000 figure 9-6. port h data direction register (ddrh) address: $0026 bit 7654321bit 0 read: kwieh7 kwieh6 kwieh5 kwieh4 kwieh3 kwieh2 kwieh1 kwieh0 write: reset:00000000 figure 9-7. port h key wakeup interrupt enable register (kwieh) address: $0027 bit 7654321bit 0 read: kwifh7 kwifh6 kwifh5 kwifh4 kwifh3 kwifh2 kwifh1 kwifh0 write: reset:00000000 figure 9-8. port h key wakeup flag register (kwifh) key wakeup registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 97 9.2.9 port j data register read: anytime write: anytime port j is associated with key wakeup j. key wakeup s can be used with the pins designated as inputs or outputs. ddrj determines whethe r each pin is an input or output. 9.2.10 port j data direction register determines direction of each port j pin. ddrj7?ddrj0 ? data direction port j bits 1 = associated pin is an output. 0 = associated pin is an input. 9.2.11 port j key wakeup interrupt enable register read: anytime write: anytime an interrupt is generated when a bit in the kwifj register and its corresponding kwiej bit are both set. these bits correspond to the pins of port j. al l eight bits/pins share the same interrupt vector. kwiej7?kwief0 ? key wakeup port j interrupt enable bits 1 = interrupt for the associated bit is enabled. 0 = interrupt for the associated bit is disabled. address: $0028 bit 7654321bit 0 read: pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 write: reset:00000000 alternate pin function: kwj7 k wj6 kwj5 kwj2 kwj4 kwj2 kwj1 kwj0 figure 9-9. port j data register (portj) address: $0029 bit 7654321bit 0 read: ddrj7 ddrj6 ddrj5 ddrj4 ddrj3 ddrj2 ddrj1 ddrj0 write: reset:00000000 figure 9-10. port j data direction register (ddrj) address: $002a bit 7654321bit 0 read: kwiej7 kwiej6 kwiej5 kwiej4 kwiej3 kwiej2 kwiej1 kwiej0 write: reset:00000000 figure 9-11. port j key wakeup interrupt enable register (kwiej) key wakeups mc68hc812a4 data sheet, rev. 7 98 freescale semiconductor 9.2.12 port j k ey wakeup flag register read: anytime write: anytime each flag gets set by an active edge on the associat ed input pin. this could be a rising or falling edge based on the state of the kpolj register. to clear the flag, write 1 to the corresponding bit in kwifj. initialize this register afte r initializing kpolj so that illegal flags can be cleared. kwifj7?kwifj0 ? key wakeup port j flags 1 = an active edge on the associated bit has occurred. an interrupt occurs if the associated enable bit is set. 0 = an active edge on the associated bit has not occurred. 9.2.13 port j key wakeup polarity register read: anytime write: anytime it is best to clear the flags after initializing this re gister because changing the polarity of a bit can cause the associated flag to set. kpolj7?kpolj0 ? key wakeup port j polarity select bits 1 = rising edge on the associated port j pin sets the associated flag bit in the kwifj register. 0 = falling edge on the associated port j pin sets the associated flag bit in the kwifj register. address: $002b bit 7654321bit 0 read: kwifj7 kwifj6 kwifj5 kwifj4 kwifj3 kwifj2 kwifj1 kwifj0 write: reset:00000000 figure 9-12. port j key wakeup flag register (kwifj) address: $002c bit 7654321bit 0 read: kpolj7 kpolj6 kpolj5 kpolj4 kpolj3 kpolj2 kpolj1 kpolj0 write: reset:00000000 figure 9-13. port j key wakeup polarity register (kpolj) key wakeup registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 99 9.2.14 port j pullup/p ulldown select register read: anytime write: anytime each bit in the register corresponds to a port j pin. each bit selects a pullup or pulldown device for the associated port j pin. the pullup or pulldown is active only if enabled by the pulej register. pupsj should be initialized before enabl ing the pullups/pul ldowns (pupej). pupsj7?pupsj0 ? key wakeup port j pullup/pulldown select bits 1 = pullup is selected for the associated port j pin. 0 = pulldown is selected for the associated port j pin. 9.2.15 port j pullup /pulldown enable register read: anytime write: anytime each bit in the register corresponds to a port j pin. if a pin is configured as an input, each bit enables an active pullup or pulldown device. pupsj selects wh ether a pullup or a pulldown is the active device. pulej7?pulej0 ? key wakeup port j pullup/pulldown enable bits 1 = selected pullup/pulldown device for the associ ated port j pin is enabled if it is an input. 0 = associated port j pin has no pullup/pulldown device. address: $002d bit 7654321bit 0 read: pupsj7 pupsj6 pupsj5 pupsj4 pupsj3 pupsj2 pupsj1 pupsj0 write: reset:00000000 figure 9-14. port j pullup/pulldown select register (pupsj) address: $002e bit 7654321bit 0 read: pulej7 pulej6 pulej5 pulej4 pulej3 pulej2 pulej1 pulej0 write: reset:00000000 figure 9-15. port j pullup/pulldown enable register (pulej) key wakeups mc68hc812a4 data sheet, rev. 7 100 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 101 chapter 10 clock module 10.1 introduction clock generation circuitry generates the internal and exte rnal e-clock signals as well as internal clock signals used by the cpu and on-chip peripherals. a cl ock monitor circuit, a com puter operating properly (cop) watchdog circuit, and a periodic interrupt circuit are also incorporated into the mcu. 10.2 block diagram figure 10-1. clock module block diagram 10.2.1 clock generators the clock module generates four types of inte rnal clock signals derived from the oscillator: 1. t-clocks ? drives the cpu 2. e-clock ? drives the bus interfaces, bdm, spi, and atd 3. p-clock ? drives the bus interfaces, bdm, spi, and atd 4. m-clock ? drives on-chip modules such as the timer, sci, rti, cop, and restart-from-stop delay time 0:1:1 extal xtal 0:0:0 0:0:1 0:1:0 1:0:0 1:0:1 1:1:0 1:1:1 sysclk eclk pclk mclk tclk 2 2 2 2 2 2 2 2 oscillator phase-lock loop plls to cpu t-clock generator e- and p-clock generator muxclk 0:0 0:1 1:0 2 2 2 register: clkctl bits: mcs[b:a] register: clkctl bits: bcs[c:b:a] to bdm, buses, spi, atd to sci, tim, pa, rti, cop 1:1 2 clock module mc68hc812a4 data sheet, rev. 7 102 freescale semiconductor figure 10-2 shows clock timing relationships. four bits in the clkctl register control the base clock and m-clock divide selection ( 1, 2, 4, and 8 are selectable). figure 10-2. internal clock relationships 10.3 register map note the register block can be mapped to any 2-kbyte boundary within the standard 64-kbyte address space. the r egister block occupies the first 512 bytes of the 2-kbyte block. this register map shows default addressing after reset. addr.register name bit 7654321bit 0 $0014 real-time interrupt control reg. (rtictl) see page 105. read: rtie rswai rsbck 0 rtbyp rtr2 rtr1 rtr0 write: reset:00000000 $0015 real-time interrupt flag register (rtiflg) see page 107. read: rtif 0000000 write: reset:00000000 $0016 cop control register (copctl) see page 107. read: cme fcme fcm fcop disr cr2 cr1 cr0 write: reset:00000000 $0017 arm/reset cop register (coprst) see page 109. read: 0 0 0 00000 write: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset:00000000 = unimplemented figure 10-3. clock function register map t1clk t2clk t3clk t4clk internal eclk pclk mclk note: the mclk depends on the chosen divider settings in the clkctl register. 8 mclk 4 mclk 2 mclk 1 functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 103 10.4 functional description this section provides a functional description of the mc68hc812a4. 10.4.1 computer oper ating properly (cop) the cop or watchdog timer is an added check that a program is running and sequencing properly. when the cop is being used, software is responsible for keeping a free-running watchdog timer from timing out. if the watchdog timer times out, it is an indication that the software is no longer being executed in the intended sequence; thus, a system reset is initiated. three control bits allow selection of seven cop timeout periods. when cop is enabled , sometime during the selected period the program must write $55 and $aa (in this order) to the coprst register. if the program fails to do this, the part resets. if any value other than $55 or $aa is written, the part resets. 10.4.2 real-time interrupt there is a real-time (periodic) interrupt (rti) availabl e to the user. this interrupt occurs at one of seven selected rates. an interrupt flag and an interrupt enabl e bit are associated with this function. the rate select has three bits. 10.4.3 clock monitor the clock monitor circuit is based on an internal resi stor-capacitor (rc) time delay. if no mcu clock edges are detected within this rc time delay, the clock monitor can generate a system reset. the clock monitor function is enabled/disabled by the cm e control bit in the copctl regist er. this timeout is based on an rc delay so that the clock monitor can operate without any mcu clocks. cme enables clock monitor. 1 = slow or stopped clocks (including the st op instruction) cause a clock reset sequence. 0 = clock monitor is disabled. slow clocks and stop instruction may be used. clock monitor timeouts are shown in table 10-1 . 10.4.4 peripheral clock divider chains figure 10-4 , figure 10-5 , and figure 10-6 summarize the peripheral clock divider chains. table 10-1. clock monitor timeouts supply range 5 v 10% 2?20 s 3 v 10% 5?100 s clock module mc68hc812a4 data sheet, rev. 7 104 freescale semiconductor figure 10-4. clock chain for sci0, sci1, rti, and cop figure 10-5. clock chain for tim 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 0:0:0 0:0:1 0:1:0 0:1:1 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 4 4 4 4 4 4 1:0:0 sci0 receive baud rate (16x) sci0 transmit baud rate (1x) sci0 baud rate generator (3 1 to 8191) register: rtictl bits: rtr[2:1:0] register: copctl bits: cr[2:1:0] 8192 16 sci1 receive baud rate (16x) sci1 transmit baud rate (1x) sci1 baud rate generator (3 1 to 8191) 16 mclk to rti to cop mclk port t7 paclk paclk (paov) ten 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 register: tmsk2 bits: pr[2:0] pamod 2 2 2 2 2 2 gate logic paen pulse accumulator low byte pulse accumulator high byte 1:0:0 1:0:1 1:1:0 1:1:1 register: pactl bits: paen:clk1:clk0 0:x:x to tim counter 65,536 paclk 256 registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 105 figure 10-6. clock chain for spi, atd, and bdm 10.5 registers and reset initialization this section describes the registers and reset initialization. 10.5.1 real-time interr upt control register read: anytime write: varies from bit to bit address: $0014 bit 7654321bit 0 read: rtie rswai rsbck 0 rtbyp rtr2 rtr1 rtr0 write: reset:00000000 = unimplemented figure 10-7. real-time interrupt control register (rtictl) pclk bkgd out bkgd 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 2 2 2 2 2 2 spi bit rate register: sp0br bits: spr2:spr1:spr0 0:0:0 bdm bit clock receive: detect falling edge; count 12 e-clocks; sample input transmit 1: detect falling edge; count six e-clocks while output is high impedance; drive out one e cycle pulse high; return output to high impedance transmit 0: detect falling edge; dr ive out low; count nine e-clocks; drive out one e cycle pulse high; return output to high-impedance prs[4:0] 5-bit atd prescaler 2 atd clock bkgd pin logic synchronizer 2 eclk direction bkgd in clock module mc68hc812a4 data sheet, rev. 7 106 freescale semiconductor rtie ? real-time interrupt enable bit write: anytime rtie enables interrupt requests generated by the rtif flag. 1 = rtif interrupt requests enabled 0 = rtif interrupt requests disabled rswai ? rti stop in wait bit write: once in normal modes, anytime in special modes rswai disables the rti and the cop during wait mode. 1 = rti and cop disabled in wait mode 0 = rti and cop enabled in wait mode rsbck ? rti stop in background mode bit write: once in normal modes, anytime in special modes rsbck disables the rti and the cop during background debug mode. 1 = rti and cop disabled during background mode 0 = rti and cop enabled during background mode rtbyp ? rti bypass bit write: never in normal modes, anytime in special modes rtbyp allows faster testing by causing the divider chain to be bypassed. the divider chain normally divides m by 2 13 . when rtbyp is set, the divi der chain divides m by 4. 1 = divider chain bypass 0 = no divider chain bypass rtr2, rtr1, rtr0 ? real-time interrupt rate select bits write: anytime rate select for real-time interrupt. the clock us ed for this module is the module (m) clock. table 10-2. real-time interrupt rates rtr[2:1:0] m-clock divisor real-time timeout period m = 4.0 mhz m = 8.0 mhz 000 off off off 001 2 13 2.048 ms 1.024 ms 010 2 14 4.096 ms 2.048 ms 011 2 15 8.196 ms 4.096 ms 100 2 16 16.384 ms 8.196 ms 101 2 17 32.768 ms 16.384 ms 110 2 18 65.536 ms 32.768 ms 111 2 19 131.72 ms 65.536 ms registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 107 10.5.2 real-time in terrupt flag register rtif ? real-time interrupt flag rtif is set when the timeout period elapses. rtif generates an interrupt request if the rtie bit is set in the rti control register. clear rtif by writing to the real-time interrupt flag register with rtif set. 1 = timeout period elapsed 0 = timeout period not elapsed 10.5.3 cop control register read: anytime write: varies from bit to bit cme ? clock monitor enable bit write: anytime cme enables the clock monitor. if the force cl ock monitor enable bit, fcme, is set, cme has no meaning or effect. 1 = clock monitor enabled 0 = clock monitor disabled note clear the cme bit before executing a stop instruction and set the cme bit after exiting stop mode. fcme ? force clock monitor enable bit write: once in normal modes, anytime in special modes fcme forces the clock monitor to be enabled unti l a reset occurs. when fcme is set, the cme bit has no effect. 1 = clock monitor enabled 0 = cme bit enables or disables clock monitor note clear the fcme bit in applications that use the stop instruction and the clock monitor. address: $0015 bit 7654321bit 0 read: rtif 0000000 write: reset:00000000 = unimplemented figure 10-8. real-time interrupt flag register (rtiflg) address: $0016 bit 7654321bit 0 read: cme fcme fcm fcop disr cr2 cr1 cr0 write: reset:00000000 figure 10-9. cop control register (copctl) clock module mc68hc812a4 data sheet, rev. 7 108 freescale semiconductor fcm ? force clock monitor reset bit write: never in normal modes, anytime in special modes fcm forces a reset when the clock monitor is enabled and detects a slow or stopped clock. 1 = clock monitor reset enabled 0 = normal operation note when the disable reset bit, disr, is set, fcm has no effect. fcop ? force cop reset bit write: never in normal modes; anytime in special modes fcop forces a reset when the cop is enabled and times out. 1 = cop reset enabled 0 = normal operation note when the disable reset bit, disr, is set, fcop has no effect. disr ? disable reset bit write: never in normal modes; anytime in special modes disr disables clock monitor resets and cop resets. 1 = clock monitor and cop resets disabled 0 = normal operation cr2, cr1, and cr0 ? cop watchdog timer rate select bits write: once in normal modes, anytime in special modes the cop system is driven by a constant frequency of m/2 13 . these bits specify an additional division factor to arrive at the cop timeout rate. (the clock used for this module is the m-clock.) table 10-3. cop watchdog rates cr[2:1:0] m-clock divisor cop timeout period 0/+2.048 ms 0/+1.024 ms m = 4.0 mhz m = 8.0 mhz 000 off off off 001 2 13 2.048 ms 1.024 ms 010 2 15 8.1920 ms 4.096 ms 011 2 17 32.768 ms 16.384 ms 100 2 19 131.072 ms 65.536 ms 101 2 21 524.288 ms 262.144 ms 110 2 22 1.048 s 524.288 ms 111 2 23 2.097 s 1.048576 s registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 109 10.5.4 arm/reset cop timer register to restart the cop timeout period and avoid a cop reset, write $55 and then $aa to this address before the end of the cop timeout period. other instruct ions can be executed between these writes. writing anything other than $55 or $aa causes a cop reset to occur. address: $0017 bit 7654321bit 0 read:00000000 write: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset:00000000 figure 10-10. arm/reset cop timer register (coprst) clock module mc68hc812a4 data sheet, rev. 7 110 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 111 chapter 11 phase-lock loop (pll) 11.1 introduction the phase-lock loop (pll) allows slight adjustments in the frequency of the mcu. the smallest increment of adjustment is 9.6 khz to the output frequency (f out ) rate assuming an input clock of 16.8 mhz (oscxtal) and a reference divider set to 1750. figure 11-1 shows the pll dividers and a portion of the clock module and figure 11-2 provides a register map. 11.2 block diagram figure 11-1. pll block diagram eclk & pclk generator mux ldv[11:0] module clock divider loop divider reference divider out-of-lock detector phase detector vco tclk generator base clock divider oscillator extal pin charge pump xfc pin v ddpll pllon plls f reference f loop up down lckf muxclk bcs[c:b:a] sysclk pclk eclk to mpu rdv[11:0] tclk to cpu mcs[b:a] to modules xtal pin mclk c s r s c p loop filter see table 11-1 2 phase-lock loop (pll) mc68hc812a4 data sheet, rev. 7 112 freescale semiconductor 11.3 register map table 11-1. pll filter values r s e clock c s crystal 16,778.40524 8,000,000 0.000000033 32,000 11,864.12412 8,000,000 0.000000033 64,000 3,001.412373 8,000,000 0.000000033 1,000,000 2,450.642941 8,000,000 0.000000033 1,500,000 2,237.120698 8,000,000 0.000000033 1,800,000 2,122.319042 8,000,000 0.000000033 2,000,000 1,898.259859 8,000,000 0.000000033 2,500,000 1,732.866242 8,000,000 0.000000033 3,000,000 1,604.322397 8,000,000 0.000000033 3,500,000 1,500.706187 8,000,000 0.000000033 4,000,000 1,355.8999 8,000,000 0.000000033 4,900,000 1,342.272419 8,000,000 0.000000033 5,000,000 c p = .0033 f addr.register name bit 7654321bit 0 $0040 loop divider register high (ldvh) see page 113. read: 0 0 0 0 ldv11 ldv10 ldv9 ldv8 write: reset:00001111 $0041 loop divider register low (ldvl) see page 113. read: ldv7 ldv6 ldv5 ldv4 ldv3 ldv2 ldv1 ldv0 write: reset:11111111 $0042 reference divider register high (rdvh) see page 114. read: 0 0 0 0 rdv11 rdv10 rdv9 rdv8 write: reset:00001111 $0043 reference divider register low (rdvl) see page 114. read: rdv7 rdv6 rdv5 rdv4 rdv3 rdv2 rdv1 rdv0 write: reset:11111111 $0047 clock control register (clkctl) see page 114. read: lckf pllon plls bcsc bcsb bcsa mcsb mcsa write: reset:00000000 = unimplemented figure 11-2. pll register map functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 113 11.4 functional description the pll may be used to run the mcu from a different timebase than the incoming crystal value. if the pll is selected, it continues to run when it?s in wait or stop mode which results in more power consumption than normal. to take full advantage of the reduced power consumption of stop mode, turn off the pll before going into stop. although it is possible to set the divider to comm and a very high clock frequency, do not exceed the 16.8 mhz frequency limit for the mcu. a passive external loop filter must be placed on the control line (xfc pad). the filter is a second-order, low-pass filter to eliminate the vco input ripple. 11.5 registers and reset initialization this section describes the registers and reset initialization. 11.5.1 loop divider registers read: anytime write: anytime if the pll is on, the count in the loop divider (ldv) 12- bit register effectively multiplies up from the pll base frequency. caution do not exceed the maximum rated operating frequency for the cpu. address: $0040 bit 7654321bit 0 read:0000 ldv11 ldv10 ldv9 ldv8 write: reset:00001111 = unimplemented figure 11-3. loop divider register high (ldvh) address: $0041 bit 7654321bit 0 read: ldv7 ldv6 ldv5 ldv4 ldv3 ldv2 ldv1 ldv0 write: reset:11111111 figure 11-4. loop divider register low (ldvl) phase-lock loop (pll) mc68hc812a4 data sheet, rev. 7 114 freescale semiconductor 11.5.2 reference divider registers read: anytime write: anytime the count in the reference divider (rdv) 12-bit register divides the crystal oscillator clock input. in the reset condition, both ldv and rdv are set to the maximum count which produces an internal frequency at the phase detector of 8.2 khz and a fi nal output frequency of 16.8 mhz with a 16.8 mhz input clock. 11.5.3 clock control register read: anytime write: anytime lckf ? lock flag this read-only flag is set when the pll frequency is at least half the target frequency and no more than twice the target frequency. 1 = pll locked 0 = pll not locked pllon ? pll on bit setting pllon turns on the pll. 1 = pll on 0 = pll off address: $0042 bit 7654321bit 0 read:0000 rdv11 rdv10 rdv9 rdv8 write: reset:00001111 = unimplemented figure 11-5. reference divider register high (rdvh) address: $0043 bit 7654321bit 0 read: rdv7 rdv6 rdv5 rdv4 rdv3 rdv2 rdv1 rdv0 write: reset:11111111 figure 11-6. reference divider register low (rdvl) address: $0047 bit 7654321bit 0 read: lckf pllon plls bcsc bcsb bcsa mcsb mcsa write: reset:00000000 = unimplemented figure 11-7. clock control register (clkctl) registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 115 plls ? pll select bit (pll output or crystal input frequency) plls selects the pll after the lckf flag is set. 1 = pll selected 0 = crystal input selected bcs[c:b:a] ? base clock select bits these bits determine the frequency of sysclk. sysclk is the source clock for the mcu, including the cpu and buses. see table 11-2 . sysclk and is twice the bus rate. muxclk is either the pll output or the crystal input frequency as selected by the plls bit. mcsa and mcsb ? module clock select bits these bits determine the clock used by some sections of some of the modules such as the baud rate generators of the scis, the timer counter, the rti, and cop. see table 11-3 . mclk is the module clock and pclk is an internal bus rate clock. the bcsx and mcsx bits can be ch anged with a single-write access. in combination, these bits can be used to ?throttle? the cpu clock rate without affe cting the mclk rate; timing and baud rates can remain constant as the processor speed is changed to match sy stem requirements. this can save overall system power. table 11-2. base clock selection bcsc:bcsb:bcsa sysclk 000 muxclk 001 010 011 100 101 110 111 table 11-3. module clock selection mcs[b:a] mclk 00 pclk 01 10 11 muxclk 2 ------------------------ - muxclk 4 ------------------------ - muxclk 8 ------------------------ - muxclk 16 ------------------------ - muxclk 32 ------------------------ - muxclk 64 ------------------------ - muxclk 128 ------------------------ - pclk 2 ---------------- pclk 4 ---------------- pclk 8 ---------------- phase-lock loop (pll) mc68hc812a4 data sheet, rev. 7 116 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 117 chapter 12 standard timer module 12.1 introduction the standard timer module is a 16-bit, 8-channel timer with: input capture output compare pulse accumulator functions a block diagram is given in figure 12-1 . 12.2 register map a summary of the input/oputput (i/o) registers is shown in figure 12-2 . note the register block can be mapped to any 2-kbyte boundary within the standard 64-kbyte address space. the r egister block occupies the first 512 bytes of the 2-kbyte block. this register map shows default addressing after reset. in normal modes, writing to a reserved bit has no effect and reading returns logic 0. in any mode, writing to an unimplemented bit has no effect and reading returns a logic 0. standard timer module mc68hc812a4 data sheet, rev. 7 118 freescale semiconductor 12.3 block diagram figure 12-1. timer block diagram prescaler channel 0 pt0 16-bit counter module logic pr[2:1:0] divide-by-64 module clock timc0h:timc0l edge detect timpacnth:timpacntl paovf pedge paovi pamod pae 16-bit comparator timcnth:timcntl 16-bit latch channel 1 timc1h:timc1l 16-bit comparator 16-bit latch 16-bit counter interrupt logic tof toi c0f c1f edge detect pt1 logic edge detect cxf channels 2?6 channel 7 timc7h:timc7l 16-bit comparator 16-bit latch c7f pt7 logic edge detect ios0 ios1 ios7 om0 ol0 om1 ol1 om7 ol7 edg1a edg1b edg7a edg7b edg0a edg0b tcre channel 7 output compare paif clear counter paif pai interrupt logic cxi interrupt request interrupt request paovf ch. 7 compare ch. 7 capture ch. 1 capture mux clk[1:0] paclk paclk/256 paclk/65536 pad pad pad paclk paclk/256 paclk/65536 te clock ch. 1 compare ch. 0 compare ch. 0 capture pa input block diagram mc68hc812a4 data sheet, rev. 7 freescale semiconductor 119 addr.register name bit 7654321bit 0 $0080 timer ic/oc select register (tios) see page 125. read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: reset:00000000 $0081 timer compare force register (cforc) see page 125. read: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 write: reset:00000000 $0082 timer output compare 7 mask register (oc7m) see page 126. read: oc7m7oc7m6oc7m5oc7m4oc7m3oc7m2oc7m1oc7m0 write: reset:00000000 $0083 timer output compare 7 data register (oc7d) see page 126. read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: reset:00000000 $0084 timer counter register high (tcnth) see page 127. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0085 timer counter register low (tcntl) see page 127. read: bit 7 6 5 4321bit 0 write: reset:00000000 $0086 timer system control register (tscr) see page 127. read: ten tswai tsbck tffca 0000 write: reset:00000000 $0087 reserved rrrrrrrr $0088 timer control register 1 (tctl1) see page 129. read: om7ol7om6ol6om5ol5om4ol4 write: reset:00000000 $0089 timer control register 2 (tctl2) see page 129. read: om3ol3om2ol2om1ol1om0ol0 write: reset:00000000 $008a timer control register 3 (tctl3) see page 130. read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: reset:00000000 $008b timer control register 4 (tctl4) see page 130. read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: reset:00000000 $008c timer mask register 1 (tmsk1) see page 130. read: c7ic6ic5ic4ic3ic2ic1ic0i write: reset:00000000 = unimplemented r = reserved figure 12-2. i/o register summary (sheet 1 of 4) standard timer module mc68hc812a4 data sheet, rev. 7 120 freescale semiconductor $008d timer mask register 2 (tmsk2) see page 131. read: toi 0 pupt rdpt tcre pr2 pr1 pr0 write: reset:00110000 $008e timer flag register 1 (tflg1) see page 132. read: c7f c6f c5f c4f c3f c2f c1f c0f write: reset:00000000 $008f timer flag register 2 (tflg2) see page 132. read: tof 0000000 write: reset:00000000 $0090 timer channel 0 register high (tc0h) see page 133. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0091 timer channel 0 register low (tc0l) see page 133. read: bit 7654321bit 0 write: reset:00000000 $0092 timer channel 1 register high (tc1h) see page 133. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0093 timer channel 1 register low (tc1l) see page 133. read: bit 7654321bit 0 write: reset:00000000 $0094 timer channel 2 register high (tc2h) see page 133. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0095 timer channel 2 register low (tc2l) see page 133. read: bit 7654321bit 0 write: reset:00000000 $0096 timer channel 3 register high (tc3h) see page 133. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0097 timer channel 3 register low (tc3l) see page 133. read: bit 7654321bit 0 write: reset:00000000 $0098 timer channel 4 register high (tc4h) see page 133. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 12-2. i/o register summary (sheet 2 of 4) block diagram mc68hc812a4 data sheet, rev. 7 freescale semiconductor 121 $0099 timer channel 4 register low (tc4l) see page 133. read: bit 7654321bit 0 write: reset:00000000 $009a timer channel 5 register high (tc5h) see page 133. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $009b timer channel 5 register low (tc5l) see page 133. read: bit 7654321bit 0 write: reset:00000000 $009c timer channel 6 register high (tc6h) see page 133. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $009d timer channel 6 register low (tc6l) see page 133. read: bit 7654321bit 0 write: reset:00000000 $009e timer channel 7 register high (tc7h) see page 133. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $009f timer channel 7 register low (tc7l) see page 133. read: bit 76543210 write: reset:00000000 $00a0 pulse accumulator control register (pactl) see page 134. read: 0 paen pamod pedge clk1 clk0 paovi pai write: reset:00000000 $00a1 pulse accumulator flag register (paflg) see page 135. read: 0 0 0 0 0 0 paovf paif write: reset:00000000 $00a2 pulse accumulator counter register high (pacnth) see page 136. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $00a3 pulse accumulator counter register low (pacntl) see page 136. read: bit 7654321bit 0 write: reset:00000000 $00ad timer test register (timtst) see page 137. read: 0 0 0 0 0 0 tcbyp pcbyp write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 12-2. i/o register summary (sheet 3 of 4) standard timer module mc68hc812a4 data sheet, rev. 7 122 freescale semiconductor 12.4 functional description this section provides a functional description of the standard timer. 12.4.1 prescaler the prescaler divides the module clock by 1, 2, 4, 8, 16, or 32. the prescaler select bits, pr2, pr1, and pr0, select the prescaler divisor. pr2, pr1, and pr0 are in the timer mask 2 register (tmsk2). 12.4.2 input capture clearing the i/o (input/output) select bit, iosx, configures channel x as an input capture channel. the input capture function captures the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the timer tran sfers the value in the timer counter into the timer channel registers, timcxh and timcxl. in 8-bit mcus, the low byte of the timer channel regi ster (timcxl) is held for one bus cycle after the high byte (timcxh) is read. this allo ws coherent reading of the timer channel such that an input capture does not occur between two back-to-back 8-bit reads. to read the 16-bit timer channel register, use a double-byte read instruction such as ldd or ldx. the minimum pulse width for the input captur e input is greater than two module clocks. the input capture function does not force data directi on. the timer port data direction register controls the data direction of an input capture pin. pin conditi ons can trigger an input capture on a pin configured as an input. software can trigger an input capture on an input capture pin configured as an output. an input capture on channel x sets the cxf flag. th e cxi bit enables the cxf flag to generate interrupt requests. 12.4.3 output compare setting the i/o select bit, iosx, c onfigures channel x as an output compare channel. the output compare function can generate a periodic pulse with a program mable polarity, duration, and frequency. when the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. an output compare on channel x sets the cxf flag. the cxi bit enables the cxf flag to generate interrupt requests. the output mode and level bits, omx and olx, select set, clear, or toggle on output compare. clearing both omx and olx disconnects the pin from the output logic. $00ae timer port data register (portt) see page 139. read: pt7 pt6 pt5 pt4 pt3 pt2 pt1 pt0 write: reset: unaffected by reset $00af timer port data direction register (ddrt) see page 140. read: bit 7554321bit 0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 12-2. i/o register summary (sheet 4 of 4) functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 123 setting a force output compare bit, focx, causes an immediate output compare on channel x. a forced output compare does not set the channel flag. an output compare on channel 7 overrides output compares on all other output compare channels. a channel 7 output compare causes any unmasked bits in the output compare 7 data register to transfer to the timer port data register. the output compare 7 mask register masks the bits in the output compare 7 data register. the timer counter reset enable bit, tcre, enables channel 7 output compares to reset the timer counter. a channel 7 output compare can reset t he timer counter even if the oc7/pai pin is being used as the pulse accumulator input. an output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. writing to the timer port bit of an output compare pin does not affect the pin state. the value written is stored in an internal latch. when the pin becomes av ailable for general-purpose output, the last value written to the bit appears at the pin. 12.4.4 pulse accumulator the pulse accumulator (pa) is a 16-bit counter that can operate in two modes: event counter mode ? counting edges of selected polarity on the pulse accumulator input pin, pai gated time accumulation mode ? counti ng pulses from a divide-by-64 clock the pa mode bit, pamod, selects the mode of operation. the minimum pulse width for the pai i nput is greater than two module clocks. 12.4.4.1 event counter mode clearing the pamod bit configures the pa for event counter operation. an active edge on the pai pin increments the pa. the pa edge bit, pedge, selects falling edges or rising edges to increment the pa. an active edge on the pai pin sets the pa input flag, paif. the pa input interrupt enable bit, pai, enables the paif flag to generate interrupt requests. note the pai input and timer channel 7 use the same pin. to use the pai input, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, om7 and ol7. also clear the channel 7 output compare 7 mask bit, oc7m7. the pa counter registers, timpacnth/l, reflect the number of active input edges on the pai pin since the last reset. the pa overflow flag, paovf, is set when the pa rolls over from $ffff to $0000. the pa overflow interrupt enable bit, paovi, enables the paovf flag to generate interrupt requests. note the pa can operate in event counter mode even when the timer enable bit, te, is clear. standard timer module mc68hc812a4 data sheet, rev. 7 124 freescale semiconductor 12.4.4.2 gated time accumulation mode setting the pamod bit configures the pa for gated time accumulation operation. an active level on the pai pin enables a divided-by-64 cloc k to drive the pa. the pa edge bit, pedge, selects low levels or high levels to enable the divided-by-64 clock. the trailing edge of the active level at the pai pin sets the pa input flag, paif. the pa input interrupt enable bit, pai, enables the paif flag to generate interrupt requests. note the pai input and timer channel 7 use the same pin. to use the pai input, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, om7 and ol7. also clear the channel 7 output compare mask bit, oc7m7. the pa counter registers, timpacnth/l reflect the num ber of pulses from the divided-by-64 clock since the last reset. note the timer prescaler generates the divided-by-64 clock. if the timer is not active, there is no divided-by-64 clock. figure 12-3. channel 7 output compare/pulse accumulator logic pad om7 ol7 channel 7 output compare pulse accumulator oc7m7 registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 125 12.5 registers and reset initialization this section describes the registers and reset initialization. 12.5.1 timer ic/oc select register read: anytime write: anytime ios7?ios0 ? input capture or output compare select bits the iosx bits enable input capture or output comp are operation for the corresponding timer channel. 1 = output compare enabled 0 = input capture enabled 12.5.2 timer compare force register read: anytime; always read $00 (1 state is transient) write: anytime foc7?foc0 ? force output compare bits setting an focx bit causes an im mediate output compare on the corresponding channel. forcing an output compare does not set the output compare flag. 1 = force output compare 0 = no effect address: $0080 bit 7654321bit 0 read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: reset:00000000 figure 12-4. timer ic/oc select register (tios) address: $0081 bit 7654321bit 0 read: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 write: reset:00000000 figure 12-5. timer compare force register (cforc) standard timer module mc68hc812a4 data sheet, rev. 7 126 freescale semiconductor 12.5.3 timer output co mpare 7 mask register read: anytime write: anytime oc7m7?oc7m0 ? output compare 7 mask bits setting an oc7mx bit configures the corresponding timport pin to be an output. oc7mx makes the timer port pin an output regardless of the data dire ction bit when the pin is configured for output compare (iosx = 1). the oc7mx bits do not change the state of the timddr bits. 1 = corresponding timport pin output 0 = corresponding timport pin input 12.5.4 timer output co mpare 7 data register read: anytime write: anytime oc7d7?oc7d0 ? output compare data bits when a successful channel 7 output co mpare occurs, these bits transfer to the timer port data register if the corresponding oc7mx bits are set. note a successful channel 7 output compare overrides any channel 0?6 compares. for each oc7m bit that is set, the output compare action reflects the corresponding oc7d bit. address: $0082 bit 7654321bit 0 read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: reset:00000000 figure 12-6. timer output compare 7 mask register (oc7m) address: $0083 bit 7654321bit 0 read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: reset:00000000 figure 12-7. timer output compare 7 data register (oc7d) registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 127 12.5.5 timer counter registers read: anytime write: only in special modes; has no effect in normal modes use a double-byte read instruction to read the timer counter. two single-byte reads return a different value than a double-byte read. note the period of the first count after a write to the tcnt registers may be a different size because the write is not synchronized with the prescaler clock. 12.5.6 timer system control register read: anytime write: anytime ten ? timer enable bit ten enables the timer. clearing ten reduces power consumption. 1 = timer enabled 0 = timer and timer counter disabled when the timer is disabled, there is no divided-by -64 clock for the pa since the prescaler generates the m 64 clock. address: $0084 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 = unimplemented figure 12-8. timer counter register high (tcnth) address: $0085 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 12-9. timer counter register low (tcntl) address: $0086 bit 7654321bit 0 read: ten tswai tsbck tffca 0000 write: reset:00000000 = unimplemented figure 12-10. timer system control register (tscr) standard timer module mc68hc812a4 data sheet, rev. 7 128 freescale semiconductor tswai ? timer stop in wait mode bit tswai disables the timer and pa in wait mode. 1 = timer and pa disabled in wait mode 0 = timer and pa enabled in wait mode note if timer and pa interrupt requests are needed to bring the mcu out of wait mode, clear tswai before executing the wait instruction. tsbck ? timer stop in background mode bit tsbck stops the timer during background mode. 1 = timer disabled in background mode 0 = timer enabled in background mode note setting tsbck does not stop the pa when it is in event counter mode. tffca ? timer fast flag clear-all bit when tffca is set: ? an input capture read or a write to an out put compare channel clears the corresponding channel flag, cnf. ? any access of the timer counter regi sters, tcnth/l, clears the tof flag. ? any access of the pa counter registers, pacnth/l, clears both the paovf and paif flags in the paflg register. when tffca is clear, writing logic 1s to the flags clears them. 1 = fast flag clearing 0 = normal flag clearing figure 12-11. fast clear flag logic clear write tcx registers read tcx registers tffca data bit n write tflg1 register cnf cnf flag registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 129 12.5.7 timer contro l registers 1 and 2 read: anytime write: anytime omx/olx ? output mode/output level bits these bit pairs select the output action to be taken as a result of a successful output compare. when either omx or olx is set and the iosx bit is set, the pin is an output regardless of the state of the corresponding ddrt bit. channel 7 shares a pin with the pulse accumulator input pin. to use the pai input, clear both the om7 and ol7 bits and clear the oc7m7 bit in the output compare 7 mask register. address: $0088 bit 7654321bit 0 read: om7ol7om6ol6om5ol5om4ol4 write: reset:00000000 figure 12-12. timer control register 1 (tctl1) address: $0089 bit 7654321bit 0 read: om3ol3om2ol2om1ol1om0ol0 write: reset:00000000 figure 12-13. timer control register 2 (tctl2) table 12-1. selection of output compare action omx:olx action on output compare 00 timer disconnected from output pin logic 01 toggle ocn output line 10 clear ocn output line 11 set ocn output line standard timer module mc68hc812a4 data sheet, rev. 7 130 freescale semiconductor 12.5.8 timer contro l registers 3 and 4 read: anytime write: anytime edgnb, edgna ? input capture edge control bits these eight bit pairs configure the input capture edge detector circuits. 12.5.9 timer mask register 1 read: anytime write: anytime c7i?c0i ? channel interrupt enable bits these bits enable the flags in timer flag register 1. 1 = corresponding channel interrupt requests enabled 0 = corresponding channel interrupt requests disabled address: $008a bit 7654321bit 0 read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: reset:00000000 figure 12-14. timer control register 3 (tctl3) address: $008b bit 7654321bit 0 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: reset:00000000 figure 12-15. timer control register 4 (tctl4) table 12-2. input capture edge selection edgnb:edgna edge selection 00 input capture disabled 01 input capture on rising edges only 10 input capture on falling edges only 11 input capture on any edge (rising or falling) address: $008c bit 7654321bit 0 read: c7i c6i c5i c4i c3i c2i c1i c0i write: reset:00000000 figure 12-16. timer mask 1 register (tmsk1) registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 131 12.5.10 timer mask register 2 read: anytime write: anytime toi ? timer overflow interrupt enable bit toi enables interrupt requests generated by the tof flag. 1 = tof interrupt requests enabled 0 = tof interrupt requests disabled pupt ? port t pullup enable bit pupt enables pullup resistors on the timer port pins when the pins are configured as inputs. 1 = pullup resistors enabled 0 = pullup resistors disabled rdpt ? port t reduced drive bit rdpt reduces the output driver size for lower current and less noise. 1 = output drive reduction enabled 0 = output drive reduction disabled tcre ? timer counter reset enable bit tcre allows the counter to be reset by a channel 7 output compare. 1 = counter reset enabled 0 = counter reset disabled note when the timer channel 7 registers contain $0000 and tcre is set, the timer counter registers remain at $0000 all the time. when the timer channel 7 registers contain $ffff and tcre is set, tof never gets set even though the timer counter registers go from $ffff to $0000. pr2, pr1, and pr0 ? timer prescaler select bits these bits select the prescaler divisor for the timer counter. address: $008d bit 7654321bit 0 read: toi 0 pupt rdpt tcre pr2 pr1 pr0 write: reset:00100000 = unimplemented figure 12-17. timer mask 2 register (tmsk2) table 12-3. prescaler selection value pr[2:1:0] prescaler divisor 0000 1 1001 2 2010 4 3011 8 4100 16 standard timer module mc68hc812a4 data sheet, rev. 7 132 freescale semiconductor note the newly selected prescale divisor does not take effect until the next synchronized edge when all prescale counter stages equal 0. 12.5.11 timer flag register 1 read: anytime write: anytime; writing 1 clears flag; writing 0 has no effect c7f?c0f ? channel flags these flags are set when an input capture or out put compare occurs on the corresponding channel. clear a channel flag by writing a 1 to it. note when the fast flag clear-all bit, tffca, is set, an input capture read or an output compare write clears the corresponding channel flag. tffca is in the timer system control register (tscr). 12.5.12 timer flag register 2 read: anytime write: anytime; writing 1 clears flag; writing 0 has no effect 5101 32 6110 32 7111 32 address: $008e bit 7654321bit 0 read: c7f c6f c5f c4f c3f c2f c1f c0f write: reset:00000000 figure 12-18. timer flag register 1 (tflg1) address: $008f bit 7654321bit 0 read: tof 0000000 write: reset:00000000 = unimplemented figure 12-19. timer flag register 2 (tflg2) table 12-3. prescaler selection (continued) value pr[2:1:0] prescaler divisor registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 133 tof ? timer overflow flag tof is set when the timer counter rolls over from $ffff to $0000. clear tof by writing a 1 to it. 1 = timer overflow 0 = no timer overflow note when the timer channel 7 registers contain $ffff and the timer counter reset enable bit, tcre, is set, tof does not get set when the counter rolls over. note when the fast flag clear-all bit, tffca, is set, any access to the timer counter registers clears tof. 12.5.13 timer channel registers read: anytime write: output compare channel, anytime; input capture channel, no effect when a channel is configured for input capture (iosx = 0), the timer channel registers latch the value of the free-running counter when a defined transition occurs on the corresponding input capture pin. when a channel is configured for output compare (i osx = 1), the timer channel registers contain the output compare value. address: tc0h/l: tc1h/l: tc2h/l: tc3h/l: tc4h/l: tc5h/l: tc6h/l: tc7h/l: $0090/$0091 $0092/$0093 $0094/$0095 $0096/$0097 $0098/$0099 $009a/$009b $009c/$009d $009e/$009f bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 8 write: reset:00000000 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 12-20. timer channel registers (tcxh/l) standard timer module mc68hc812a4 data sheet, rev. 7 134 freescale semiconductor 12.5.14 pulse accumul ator control register read: anytime write: anytime paen ? pulse accumulator enable bit paen enables the pulse accumulator. 1 = pulse accumulator enabled 0 = pulse accumulator disabled note the pulse accumulator can operate ev en when the timer enable bit, ten, is clear. pamod ? pulse accumulator mode bit pamod selects event counter mode or gated time accumulation mode. 1 = gated time accumulation mode 0 = event counter mode pedge ? pulse accumulator edge bit pedge selects falling or rising edges on the pai pin to increment the counter. in event counter mode (pamod = 0): 1 = rising pai edge increments counter 0 = falling pai edge increments counter in gated time accumulation mode (pamod = 1): 1 = low pai input enables divided-by-64 clock to pulse accumulator and trailing rising edge on pai sets paif flag 0 = high pai input enables divided-by-64 clock to pul se accumulator and trailing falling edge on pai sets paif flag note the timer prescaler generates the divided-by-64 clock. if the timer is not active, there is no divided-by-64 clock. to operate in gated time accumulation mode: 1. apply logic 0 to the reset pin. 2. initialize registers for pulse accumulator mode test. 3. apply appropriate level on pai pin. 4. enable the timer. address: $00a0 bit 7654321bit 0 read: 0 paen pamod pedge clk1 clk0 paovi pai write: reset:00000000 = unimplemented figure 12-21. pulse accumulator control register (pactl) registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 135 clk1 and clk0 ? clock select bits clk1 and clk0 select the timer counter input clock as shown in table 12-4 . paovi ? pulse accumulator overflow interrupt enable bit paovi enables the pulse accumulator overflow fl ag, paovf, to generate interrupt requests. 1 = paovf interrupt requests enabled 0 = paovf interrupt requests disabled pai ? pulse accumulator interrupt enable bit pai enables the pulse accumulator input flag, paif, to generate interrupt requests. 1 = paif interrupt requests enabled 0 = paif interrupt requests disabled 12.5.15 pulse accumulator flag register read: anytime write: anytime; writing 1 clears the flag; writing 0 has no effect paovf ? pulse accumulator overflow flag paovf is set when the 16-bit pulse accumulator overflows from $ffff to $0000. clear paovf by writing to the pulse accumulator flag register with paovf set. 1 = pulse accumulator overflow 0 = no pulse accumulator overflow table 12-4. clock selection clk[1:0] timer counter clock (1) 1. changing the clkx bits causes an immediate change in the timer counter clock input. 00 timer prescaler clock (2) 2. when pae = 0, the timer pre scaler clock is always the tim- er counter clock. 01 paclk 10 11 address: $00a1 bit 7654321bit 0 read:000000 paov f pa if write: reset:00000000 = unimplemented figure 12-22. pulse accumulator flag register (paflg) paclk 256 ------------------- paclk 65,536 ------------------- standard timer module mc68hc812a4 data sheet, rev. 7 136 freescale semiconductor paif ? pulse accumulator input flag paif is set when the selected edge is detected at the pai pin. in event counter mode, the event edge sets paif. in gated time accumulation mode, the trailing edge of the gate signal at the pai pin sets paif. clear paif by writing to the pulse accumulator flag register with paif set. 1 = active pai input 0 = no active pai input note when the fast flag clear-all enable bit, tffca, is set, any access to the pulse accumulator counter registers clears all the flags in the paflg register. 12.5.16 pulse accumulat or counter registers read: anytime write: anytime these registers contain the number of active i nput edges on the pai pin since the last reset. use a double-byte read instruction to read the pulse accumulator counter. two single-byte reads return a different value than a double-byte read. note reading the pulse accumulator count er registers immediately after an active edge on the pai pin may miss the last count since the input has to be synchronized with the bus clock first. address: $00a2 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $00a3 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 12-23. pulse accumulator counter registers (pacnth/l) external pins mc68hc812a4 data sheet, rev. 7 freescale semiconductor 137 12.5.17 timer test register read: anytime write: only in special mode (smodn = 0) tcbyp ? timer divider chain bypass bit tcbyp divides the 16-bit free-running timer counter in to two 8-bit halves. the clock drives both halves directly and bypasses the timer prescaler. 1 = timer counter divided in half and prescaler bypassed 0 = normal operation pcbyp ? pulse accumulator divider chain bypass bit pcbyp divides the 16-bit pa counter into two 8-bi t halves. the clock drives both halves directly and bypasses the timer prescaler. 1 = pa counter divided in half and prescaler bypassed 0 = normal operation 12.6 external pins the timer has eight pins for input capture and output co mpare functions. one of th e pins is also the pulse accumulator input. all eight pins are available for general-purpose i/o when not configured for timer functions. 12.6.1 input capture/ output compare pins the iosx bits in the timer ic/oc select register conf igure the timer port pins as either output compare or input capture pins. the timer port data direction register controls the data direction of an input capture pin. external pin conditions trigger input captures on input capture pins configured as inputs. software triggers input captures on input capture pins configured as outputs. the timer port data direction register does not affect the data direction of an output compare pin. the output compare function overrides the data direction register but does not affect the state of the data direction register. address: $00ad bit 7654321bit 0 read:000000tcbyppcbyp write: reset:00000000 = unimplemented figure 12-24. timer test register (timtst) standard timer module mc68hc812a4 data sheet, rev. 7 138 freescale semiconductor 12.6.2 pulse accumulator pin setting the pae bit in the pulse accumulator control r egister enables the pulse ac cumulator input pin, pai. note the pai input and timer channel 7 use the same pin. to use the pai input, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, om7 and ol7. also clear the channel 7 output compare mask bit, oc7m7. 12.7 background debug mode if the tsbck bit is clear, background debug mode has no effect on the timer. if tsbck is set, background debug mode disables the timer. note setting tsbck does not stop the pulse accumulator when it is in event counter mode. 12.8 low-power options this section describes the three low-power modes: run mode wait mode stop mode 12.8.1 run mode clearing the timer enable bit (ten) or the puls e accumulator enable bit (paen) reduces power consumption in run mode. ten is in the timer system control register (tscr). paen is in the pulse accumulator control register (pactl). timer and puls e accumulator registers are still accessible, but clocks to the core of the timer are disabled. 12.8.2 wait mode timer and pulse accumulator operation in wait mode depend on the state of the tswai bit in the timer system control register tscr). if tswai is clear, the timer and pulse accumulator operate normally when the cpu is in wait mode. if tswai is set, timer and pulse accumulator cloc k generation ceases and the tim module enters a power-conservation state when the cpu is in wait mode. in this condition, timer and pulse accumulator registers are not accessible. setting tswai does not affect the state of the timer enable bit, ten, or the pulse accumulator enable bit, paen. 12.8.3 stop mode the stop instruction disables the timer for reduced power consumption. interrupt sources mc68hc812a4 data sheet, rev. 7 freescale semiconductor 139 12.9 interrupt sources 12.10 general-purpose i/o ports this section describes the general-purpose i/o ports. 12.10.1 timer port data register an i/o pin used by the timer defaults to general-purpos e i/o unless an internal function which uses that pin is enabled. read: anytime write: anytime pt7?pt0 ? timer port data bits data written to portt is buffered and drives the pins only when they are configured as general-purpose outputs. reading an input (data direction bit = 0) reads the pi n state; reading an output (data direction bit = 1) reads the latch. writing to a pin configured as a time r output does not change the pin state. table 12-5. timer interrupt sources interrupt source flag local enable ccr mask vector address timer channel 0 c0f c0i i bit $ffee, $ffef timer channel 1 c1f c1i i bit $ffec, $ffed timer channel 2 c2f c2i i bit $ffea, $ffeb timer channel 3 c3f c3i i bit $ffe8, $ffe9 timer channel 4 c4f c4i i bit $ffe6, $ffe7 timer channel 5 c5f c5i i bit $ffe4, $ffe5 timer channel 6 c6f c6i i bit $ffe2, $ffe3 timer channel 7 c7f c7i i bit $ffe0, $ffe1 timer overflow tof toi i bit $ffde, $ffdf pulse accumulator overflow paovf paovi i bit $ffdc, $ffdd pulse accumulator input paif pai i bit $ffda, $ffdb address: $00ae bit 7654321bit 0 read: pt7pt6pt5pt4pt3pt2pt1pt0 write: reset: unaffected by reset timer function: ic/oc7 ic/oc6 ic/oc5 ic4oc4 ic/oc3 ic/oc2 ic/oc1 ic/oc0 pa function: pai figure 12-25. timer port data register (portt) standard timer module mc68hc812a4 data sheet, rev. 7 140 freescale semiconductor note due to input synchronizer circuitry, the minimum pulse width for a pulse accumulator input or an input captur e input should always be greater than the width of two module clocks. 12.10.2 timer port da ta direction register read: anytime write: anytime bits 7?0 ? timport data direction bits these bits control the port logic of portt. reset clears the timer port data direction register, configuring all timer port pins as inputs. 1 = corresponding pin configured as output 0 = corresponding pin configured as input the timer forces the i/o state to be an output for each timer port pin associated with an enabled output compare. in these cases, the data direction bits do not change but have no effect on the direction of these pins. the ddrt reverts to controlling the i/o direct ion of a pin when the associated timer output compare is disabled. input captures do not override the ddrt settings. note by setting the iosx bit input capture configuration no matter what the state of the data direction register is, the timer forces output compare pins to be outputs and input capture pins to be inputs. table 12-6. timport i/o function in out data direction register output compare action reading at data bus reading at pin 00pin pin 0 1 pin output compare action 1 1 port data register output compare action 1 0 port data register port data register address: $00af bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 12-26. timer port data direction register (ddrt) using the output compare functi on to generate a square wave mc68hc812a4 data sheet, rev. 7 freescale semiconductor 141 12.11 using the output compare fu nction to generate a square wave this timer exercise is intended to utilize the out put compare function to generate a square wave of predetermined duty cycle and frequency. square wave frequency 1000 hz, duty cycle 50% the program generates a square wave, 50 percent duty cycle, on output compare 2 (oc2). the signal will be measured by the m68hc11 on the udlp1 board. it assumes a 8.0 mhz operating frequency for the e clock. the control registers are initialized to disable interrupts, configure for proper pin control action and also the tc2h register for desired compare va lue. the appropiate count must be calculated to achieve the desired frequency and duty cycle. for example: for a 50 percent duty, 1 khz signal each period must consist of 2048 counts or 1024 counts high and 1024 counts low. in essence a $0400 is added to generate a frequency of 1 khz. 12.11.1 sample calculati on to obtain period counts the sample calculation to obtain period counts is: for 1000 hz frequency: ? e-clock = 8 mhz ? ic/oc resolution factor = 1/(e-clock/prescaler) ? if the prescaler = 4, then output compare resolution is 0.5 s for a 1 khz, 50 percent duty cycle: ? 1/f = t = 1/1000 = 1 ms ? f for output compare = prescaler/e clock = 2 mhz figure 12-27. example waveform 12.11.2 equipment for this exercise, use the m68hc812a4evb emulation board. 12.11.3 code listing note a comment line is delimited by a semicolon. if there is no code before comment, a semicolon ( ;) must be placed in the first column to avoid assembly errors. 0.5 ms number of clocks = f * d 1 ms therefore, # clocks = (2 mhz) * (0.5 ms) = 1024 = $0400 standard timer module mc68hc812a4 data sheet, rev. 7 142 freescale semiconductor ---------------------------------------------------------------------- ; main program ; ---------------------------------------------------------------------- org $7000 ; 16k on-board ram, user code data area, ; ; start main program at $7000 main: bsr timerinit ; subroutine used to initialize the timer: ; ; output compare channel, no interrupts bsr sqwave ; subroutine to generate square wave done: bra done ; branch to itself, convinient for breakpoint ;* ----------------------------------------------------------------- ;* subroutine timerinit: initialize timer for output compare on oc2 ;* ----------------------------------------------------------------- timerinit: clr tmsk1 ; disable all interrupts movb #$02,tmsk2 ; disable overflow interrupt, disable pull-up ; ; resistor function with normal drive capability ;; and free running counter, prescaler = sys clock/4. movb #$10,tctl2 ; initialize oc2 to toggle on successful compare. movb #$04,tios ; select channel 2 to act as output compare. movw #$0400,tc2h ; load tc2 reg with initial compare value. movb #$80,tscr ; enable timer, timer runs during wait state, and ; ; while in background mode, also clear flags ; ; normally. rts ; return from subroutine ;* ------------------------------ ;* subroutine: sqwave ;* ------------------------------ sqwave: ;* ------- clearflg: ;* ------- ;* to clear the c2f flag: 1) read tflg1 when ;* c2f is set and then 2) write a logic "one" to c2f. ldaa tflg1 ; to clear oc2 flag, first it must be read, oraa #$04 ; then a "1" must be written to it staa tflg1 wtflg: brclr tflg1,#$04,wtflg; wait (polling) for c2f flag ldd tc2h ; loads value of compare from tc2 reg. addd #$0400 ; add hex value of 500us high time std tc2h ; set-up next transition time in 500 us bra clearflg ; continuously add 500 us, branch to clearflag rts ; return from subroutine end ; end of program mc68hc812a4 data sheet, rev. 7 freescale semiconductor 143 chapter 13 multiple serial interface (msi) 13.1 introduction the multiple serial interface (msi) module consis ts of three independent serial i/o interfaces: two serial communication interfaces, sci0 and sci1 one serial peripheral interface, spi0 note port s shares its pins with the multiple serial interface (msi). see 13.6 general-purpose i/o ports . 13.2 sci features serial comunication interface (sci) features include: full-duplex operation standard mark/space non-retu rn-to-zero (nrz) format 13-bit baud rate selection programmable 8-bit or 9-bit data format separately enabled transmitter and receiver separate receiver and transmitter interrupt requests two receiver wakeup methods: ? idle line wakeup ? address mark wakeup five flags with interrupt-generation capability: ? transmitter empty ? transmission complete ? receiver full ? receiver overrun ? idle receiver input receiver noise error detection receiver framing error detection receiver parity error detection for additional information, refer to chapter 14 serial communications interface module (sci) . multiple serial interface (msi) mc68hc812a4 data sheet, rev. 7 144 freescale semiconductor 13.3 spi features serial preipheral interface (spi) fetures include: full-duplex operation master mode and slave mode programmable slave-select output option programmable bidirectional data pin option interrupt-driven operation with two flags: ? transmission complete ? mode fault read data buffer serial clock with programmable polarity and phase reduced drive control for lower power consumption programmable open-drain output option for additional information, refer to chapter 15 serial peripheral interface (spi) 13.4 msi block diagram figure 13-1. multiple serial interface block diagram sci0 sci1 spi0 ddrs/ioctlr port s i/o drivers msi ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 rxd0 txd0 rxd1 txd1 miso/siso mosi/momi sck cs /ss msi register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 145 13.5 msi register map addr.register name bit 7654321bit 0 $00c0 sci 0 baud rate register high (sc0bdh) see page 168. read: btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 $00c1 sci 0 baud rate register low (sc0bdl) see page 168. read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 $00c2 sci 0 control register 1 (sc0cr1) see page 169. read: loops woms rsrc m wake ilt pe pt write: reset:00000000 $00c3 sci 0 control register 2 (sc0cr2) see page 171. read: tie tcie rie ilie te re rwu sbk write: reset:00000000 $00c4 sci 0 status register 1 (sc0sr1) see page 172. read: tdre tc rdrf idle or nf fe pf write: reset:11000000 $00c5 sci 0 status register 2 (sc0sr2) see page 173. read: 0 0 0 0000raf write: reset:00000000 $00c6 sci 0 data register high (sc0drh) see page 174. read: r8 t8 000000 write: reset: unaffected by reset $00c7 sci 0 data register low (sc0drl) see page 174. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $00c8 sci 1 baud rate register high (sc1bdh) see page 168. read: btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 $00c9 sci 1 baud rate register low (sc1bdl) see page 168. read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 $00ca sci 1 control register 1 (sc1cr1) see page 169. read: loops woms rsrc m wake ilt pe pt write: reset:00000000 $00cb sci 1 control register 2 (sc1cr2) see page 171. read: tie tcie rie ilie te re rwu sbk write: reset:00000000 = unimplemented figure 13-2. msi register map multiple serial interface (msi) mc68hc812a4 data sheet, rev. 7 146 freescale semiconductor full register descriptions can be found in chapter 14 serial communicati ons interface module (sci) and chapter 15 serial peripheral interface (spi) . $00cc sci 1 status register 1 (sc1sr1) see page 172. read: tdre tc rdrf idle or nf fe pf write: reset:11000000 $00cd sci 1 status register 2 (sc1sr2) see page 173. read: 0 0 0 0000raf write: reset:00000000 $00ce sci 1 data register high (sc1drh) see page 174. read: r8 t8 000000 write: reset: unaffected by reset $00cf sci 1 data register low (sc1drl) see page 174. read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $00d0 spi 0 control register 1 (sp0cr1) see page 186. read: spie spe swom mstr cpol cpha ssoe lsbf write: reset:00000000 $00d1 spi 0 control register 2 (sp0cr2) see page 187. read: 0 0 0 0 pups rds 0 spc0 write: reset:00001000 $00d2 spi 0 baud rate register (sp0br) see page 188. read: 0 0 0 0 0 spr2 spr1 spr0 write: reset:00000000 $00d3 spi 0 status register (sp0sr) see page 189. read: spif wcol 0 modf 0000 write: reset:00000000 $00d5 spi 0 data register (sp0dr) see page 190. read: bit 76543210 write: reset: unaffected by reset $00d6 port s data register (ports) see page 147. read: ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 write: reset: unaffected by reset $00d7 port s data direction register (ddrs) see page 148. read: ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented figure 13-2. msi register map (continued) general-purpose i/o ports mc68hc812a4 data sheet, rev. 7 freescale semiconductor 147 13.6 general-purpose i/o ports port s shares its pins with the multiple serial in terface (msi). in all modes , port s pins ps7?ps0 are available for either general-purpos e i/o or for sci and spi functions. 13.6.1 port s data register read: anytime write: anytime ps7?ps4 ? port s data bits 7?4 port s shares ps7?ps4 with spi0. ss is the spi0 slave-select terminal. sck is the spi0 serial clock terminal. mosi is the spi0 master out, slave in terminal. miso is the spi0 master in, slave out terminal. ps3?ps0 ? port s data bits 3?0 port s shares ps3?0 with sci1 and sci0. txd1 is the sci1 transmit terminal. rxd1 is the sci1 receive terminal. txd0 is the sci0 transmit terminal. rxd0 is the sci0 receive terminal. note reading a port s bit when its data direct ion bit is clear returns the level of the voltage on the pin. reading a port s bit when its data direction bit is set returns the level of the voltage of the pin driver input. a write to a port s bit is stored in an internal latch. the latch drives the pin only when the corresponding data direction bit is set. writes do not change the pin state when the pin is configured for sci output. address: $00d6 bit 7654321bit 0 read: ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 write: reset: unaffected by reset pin function: ss sck mosi miso txd1 rxd1 txd0 rxd0 figure 13-3. port s data register (ports) multiple serial interface (msi) mc68hc812a4 data sheet, rev. 7 148 freescale semiconductor 13.6.2 port s data direction register read: anytime write: anytime ddrs7?ddrs0 ? port s data direction bits these bits control the data direction of each port s pin. setting a ddrs bit makes the pin an output; clearing a ddrs bit makes the pin an input. reset clear s the port s data direction register, configuring all port s pins as inputs. 1 = corresponding port s pin configured as output 0 = corresponding port s pin configured as input note when the loops bit is clear, the rx pins of sci0 and sci1 are inputs and the tx pins are outputs regardless of their ddrs bits. when the spi is enabled, an spi input pin is an input regardless of its ddrs bit. when the spi is enabled, an spi output is an output only if its ddrs bit is set. when the ddrs bit of an spi output is clear, the pin is available for general-purpose i/o. 13.6.3 port s pullup a nd reduced drive control read: anytime write: anytime pups ? pullup port s enable bit setting pups enables internal pullup devices on all port s input pins. if a pin is programmed as output, the pullup device becomes inactive. 1 = pullups enabled 0 = pullups disabled address: $00d7 bit 7654321bit 0 read: ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 write: reset:00000000 figure 13-4. port s data direction register (ddrs) address: $00d1 bit 7654321bit 0 read:0000 pups rds 0 spc0 write: reset:00001000 = unimplemented figure 13-5. spi control register 2 (sp0cr2) general-purpose i/o ports mc68hc812a4 data sheet, rev. 7 freescale semiconductor 149 rds ? reduced drive port s bit setting rds lowers the drive capability of all port s output pins for lower power consumption and less noise. 1 = reduced drive 0 = full drive spc0 ? see chapter 14 serial communications interface module (sci) . 13.6.4 port s wir ed-or mode control table 13-1. port s pullup and reduced drive enable register pullups reduced drive control bit pins affected reset state control bit pins affected reset state spi control register 2 (sp0cr2) pups ps7?ps0 enabled rds ps7?ps0 disabled table 13-2. port s wired-or mode enable register control bit pins affected reset state spi control register 1 (sp0cr1) swom ps7?ps4 disabled sci0 control register 1 (sc0cr1) woms ps3, ps2 disabled sci1 control register 1 (sc1cr1) woms ps1, ps0 disabled multiple serial interface (msi) mc68hc812a4 data sheet, rev. 7 150 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 151 chapter 14 serial communications interface module (sci) 14.1 introduction the serial communications interface (sci) allows as ynchronous serial communications with peripheral devices and other mcus. 14.2 features features of the sci include: full-duplex operation standard mark/space non-retu rn-to-zero (nrz) format 13-bit baud rate selection programmable 8-bit or 9-bit data format separately enabled transmitter and receiver separate receiver and transmitter interrupt requests two receiver wakeup methods: ? idle line wakeup ? address mark wakeup five flags with interrupt-generation capability: ? transmitter empty ? transmission complete ? receiver full ? receiver overrun ? idle receiver input receiver noise error detection receiver framing error detection receiver parity error detection serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 152 freescale semiconductor 14.3 block diagram figure 14-1. sci block diagram sci data receive shift register sci data register transmit shift register register baud rate generator sbr[12:0] rxd module transmit control 316 receive and wakeup data format control control t8 pf fe nf rdrf idle tie or tcie tdre tc r8 raf loops rwu re pe ilt pt wake m clock sci ilie rie sci sci sci interrupt interrupt interrupt interrupt rsrc sbk loops te rsrc request request request request woms port s data direction register port s data reister 3 210 pin control logic txd1 rxd1 txd0 rxd0 txd rxd to sci1 txd from sci1 register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 153 14.4 register map note the register block can be mapped to any 2-kbyte boundary within the standard 64-kbyte address space. the r egister block occupies the first 512 bytes of the 2-kbyte block. this register map shows default addressing after reset. addr.register name bit 7654321bit 0 $00c0 sci 0 baud rate register high (sc0bdh) see page 168. read: btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 $00c1 sci 0 baud rate register low (sc0bdl) see page 168. read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 $00c2 sci 0 control register 1 (sc0cr1) see page 169. read: loops woms rsrc m wake ilt pe pt write: reset:00000000 $00c3 sci 0 control register 2 (sc0cr2) see page 171. read: tie tcie rie ilie te re rwu sbk write: reset:00000000 $00c4 sci 0 status register 1 (sc0sr1) see page 172. read: tdre tc rdrf idle or nf fe pf write: reset:11000000 $00c5 sci 0 status register 2 (sc0sr2) see page 173. read:0000000raf write: reset:00000000 $00c6 sci 0 data register high (sc0drh) see page 174. read: r8 t8 000000 write: reset: unaffected by reset $00c7 sci 0 data register low (sc0drl) see page 174. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $00c8 sci 1 baud rate register high (sc1bdh) see page 168. read: btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 = unimplemented figure 14-2. sci register map serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 154 freescale semiconductor $00c9 sci 1 baud rate register low (sc1bdl) see page 168. read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 $00ca sci 1 control register 1 (sc1cr1) see page 169. read: loops woms rsrc m wake ilt pe pt write: reset:00000000 $00cb sci 1 control register 2 (sc1cr2) see page 171. read: tie tcie rie ilie te re rwu sbk write: reset:00000000 $00cc sci 1 status register 1 (sc1sr1) see page 172. read: tdre tc rdrf idle or nf fe pf write: reset:11000000 $00cd sci 1 status register 2 (sc1sr2) see page 173. read:0000000raf write: reset:00000000 $00ce sci 1 data register high (sc1drh) see page 174. read: r8 t8 000000 write: reset: unaffected by reset $00cf sci 1 data register low (sc1drl) see page 174. read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented figure 14-2. sci register map (continued) functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 155 14.5 functional description the sci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices, including other mcus. the sci transmitte r and receiver operate independently, although they use the same baud rate generator. the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. 14.5.1 data format the sci uses the standard nrz mark/space data format illustrated in figure 14-3 . figure 14-3. sci data formats each data character is contained in a frame that include s a start bit, eight or nine data bits, and a stop bit. clearing the m bit in sci control register 1 configures the sci for 8-bit data characters. a frame with eight data bits has a total of 10 bits. setting the m bit conf igures the sci for 9-bit data characters. a frame with nine data bits has a total of 11 bits. setting the m bit configures the sci for 9-bit data char acters. the ninth data bit is the t8 bit in sci data register high (scdrh). it remains unchanged after transmission and can be used repeatedly without rewriting it. a frame with nine data bits has a total of 11 bits. table 14-1. example 8-bit data formats start bit data bits address bit parity bit stop bit 18001 170 2 17011 17 1 (1) 1. the address bit identifies the frame as an address character. see 14.5.4.6 receiver wakeup . 1 table 14-2. example 9-bit data formats start bit data bits address bit parity bit stop bit 19001 180 2 18011 18 1 (1) 1. the address bit identifies the frame as an address character. see 14.5.4.6 receiver wakeup . 1 bit 5 start bit bit 0 bit 1 next stop bit start bit 9-bit data format bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit parity or data bit bit m in sccr1 set 8-bit data format bit m in sccr1 clear bit 5 bit 0 bit 1 bit 2 bit 3 bit 4 bit 6 bit 7 bit 8 stop bit next start bit start bit serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 156 freescale semiconductor 14.5.2 baud rate generation a 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. the value from 0 to 8191 written to the sbr12?sbr0 bits determines the module clock divisor. the sbr bits are in the sci baud rate r egisters (scbdh and scbdl). the baud rate clock is synchronized with the bus clock and drives the receiv er. the baud rate clock divided by 16 drives the transmitter. the receiver has an acquisi tion rate of 16 samples per bit time. baud rate generation is subject to two sources of error: integer division of the module clock may not give the exact target frequency. synchonization with the bus clock can cause phase shift. table 14-3 lists some examples of achieving target baud rates with a module clock frequency of 10.2 mhz. 14.5.3 transmitter a block diagram of the sci transmitter is shown in figure 14-4 . 14.5.3.1 character length the sci transmitter can accommodate either 8-bit or 9- bit data characters. the state of the m bit in sci control register 1 (sccr1) determines the length of data characters. when transmitting 9-bit data, bit t8 in sci data register high (scdrh) is the ninth bit (bit 8). 14.5.3.2 character transmission during an sci transmission, the transmit shift register shifts a frame out to the txd pin. the sci data registers (scdrh and scdrl) are the write-only buffe rs between the internal data bus and the transmit shift register. table 14-3. baud rates (module clock = 10.2 mhz) baud rate divisor (1) 1. the baud rate divisor is the value written to the sbr12?sbr0 bits. receiver clock rate (hz) (2) 2. the receiver clock frequency is the mc lk frequency divided by the baud rate divisor. transmitter clock rate (hz) (3) 3. the transmitter clock frequency is the receiver clock frequency divided by 16. target baud rate error (%) 17 600,000.0 37,500.0 38,400 2.3 33 309,090.9 19,318.2 19,200 0.62 66 154,545.5 9659.1 9600 0.62 133 76,691.7 4793.2 4800 0.14 266 38,345.9 2396.6 2400 0.14 531 19,209.0 1200.6 1200 0.11 1062 9604.5 600.3 600 0.05 2125 4800.0 300.0 300 0.00 4250 2400.0 150.0 150 0.00 5795 1760.1 110.0 110 0.00 functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 157 figure 14-4. sci transmitter block diagram to initiate an sci transmission: 1. enable the transmitter by writing a logic 1 to t he transmitter enable bit, te, in sci control register 2 (sccr2). 2. clear the transmit data register empty flag, tdre , by first reading sci status register 1 (scsr1) and then writing to sci data register low (scdrl). in 9-data-bit format, write the ninth bit to the t8 bit in sci data register high (scdrh). 3. repeat step 2 for each subsequent transmission. writing the te bit from 0 to 1 automatically loads the tr ansmit shift register with a preamble of 10 logic 1s (if m = 0) or 11 logic 1s (if m = 1). after the preamble sh ifts out, control logic transfers the data from the sci data register into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of th e transmit shift register. a logic 1 stop bit goes into the most significant bit position. hardware supports odd or even parity. when parity is enabled, the most significant bit (msb) of the data character is the parity bit. the transmit data register empty flag, tdre, in sci status register 1 (scsr1) becomes set when the sci data register transfers a byte to the transmit shift register. the tdre flag indicates that the sci data pe pt h876543210l 11-bit transmit shift register stop start t8 tdre tie tcie sbk tc parity generation msb sci data registers load from scidr shift enable preamble (all 1s) break (all 0s) transmitter control m internal bus sbr12?sbr0 baud divider 3 16 txd sci interrupt request sci interrupt request module loop loops rsrc clock te to control receiver serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 158 freescale semiconductor register can accept new data from the internal data bus. if the transmit interrupt enable bit, tie, in sci control register 2 (sccr2) is also set, the tdre flag generates an sci interrupt request. when the transmit shift register is not transmitting a frame, the txd pin goes to the idle condition, logic 1. if at any time software clears the te bit in sci control register 2 (sccr2), the transmitter and receiver relinquish control of the port i/o pins. if software clears te while a transmission is in progre ss (tc = 0), the frame in the transmit shift register continues to shift out. then the txd pin reverts to being a general-purpose i/o pi n even if there is data pending in the sci data register. to avoid accidentally cutting off the last frame in a message, always wait for tdre to go high after the last frame before clearing te. to separate messages with preambles with mi nimum idle line time, use this sequence between messages: 1. write the last byte of the first message to scdrh/l. 2. wait for the tdre flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. queue a preamble by clearing and then setting the te bit. 4. write the first byte of the second message to scdrh/l. when the sci relinquishes the txd pin, the ports and ddrs registers control the txd pin. to force txd high when turning off the transmitter, set bit 1 of the port s register (ports) and bit 1 of the port s data direction register (ddrs). the txd pin goes high as soon as the sci relinquishes it. 14.5.3.3 break characters writing a logic 1 to the send break bit, sbk, in sci control register 2 (sccr2) loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on th e m bit in sci control register 1 (sccr1). as long as sbk is at logic 1, transmitter logic cont inuously loads break characte rs into the transmit shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. the sci recognizes a break character when a start bit is followed by eight or ni ne logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing error flag, fe sets the receive data register full flag, rdrf clears the sci data registers, scdrh/l may set the overrun flag, or, noise flag, nf, parity error flag, pe, or the receiver active flag, raf (see 14.6.4 sci status register 1 ) 14.5.3.4 idle characters an idle character contains all logic 1s and has no st art, stop, or parity bit. idle character length depends on the m bit in sci control register 1 (sccr1). the pr eamble is a synchronizing idle character that begins the first transmission initiated afte r writing the te bit from 0 to 1. if the te bit is cleared during a transmission, the txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the frame currently being transmitted. functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 159 note when queueing an idle character, return the te bit to logic 1 before the stop bit of the current frame shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the sci data register to be lost. toggle the te bit for a queued idle character when the tdre flag becomes set and immediately before writing the next byte to the sci data register. 14.5.4 receiver a block diagram of the sci receiver is shown in figure 14-5 . figure 14-5. sci receiver block diagram 14.5.4.1 character length the sci receiver can accommodate either 8-bit or 9-bit data characters. the state of the m bit in sci control register 1 (sccr1) determines the length of dat a characters. when receiving 9-bit data, bit r8 in sci data register high (scdrh) is the ninth bit (bit 8). all 1s m wake ilt pe pt re h876543210l 11-bit receive shift register stop start data wakeup parity checking msb sci data register r8 rie ilie rwu rdrf or nf fe pe internal bus rxd module sci interrupt request sci interrupt request sbr12?sbr0 baud divider loop loops rsrc from txd pin or transmitter clock idle raf recovery control logic serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 160 freescale semiconductor 14.5.4.2 character reception during an sci reception, the receive shift register shifts a frame in from the rxd pin. the sci data register is the read-only buffer between the internal data bus and the receive shift register. after a complete frame shifts into the receive shift register, the data portion of the frame transfers to the sci data register. the receive data register full flag, rdrf, in sci status register 1 (scsr1) becomes set, indicating that the received byte can be read. if t he receive interrupt enable bit, rie, in sci control register 2 (sccr2) is also set, the rdrf flag generates an interrupt request. 14.5.4.3 data sampling the receiver samples the rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock (see figure 14-6 ) is resynchronized: after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an a synchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 14-6. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 14-4 summarizes the results of the start bit verification samples. table 14-4. start bit verification rt3, rt5, and rt7 samples sta rt bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 samples rt clock rt clock count start bit rxd start bit qualification start bit data sampling 11 1 1 1 1 110000 0 00 lsb verification functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 161 if start bit verification is not successful, the rt cl ock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-5 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit (logic 0). to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 14-6 summarizes the results of the stop bit samples. in figure 14-7 the verification samples rt3 and rt5 determine that the first low detected was noise and not the beginning of a start bit. the rt clock is reset and the start bit search begins again. the noise flag is not set because the noise occurred before the start bit was found. table 14-5. data bit recovery rt8, rt9, and rt10 samples dat a bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 14-6. stop bit recovery rt8, rt9, and rt10 samples f raming error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 162 freescale semiconductor figure 14-7. start bit search example 1 in figure 14-8 noise is perceived as the beginning of a start bit although the verification sample at rt3 is high. the rt3 sample sets the noise flag. although t he perceived bit time is misaligned, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 14-8. start bit search example 2 in figure 14-9 a large burst of noise is perceived as the beginning of a start bit, although the test sample at rt5 is high. the rt5 sample sets the noise flag. although this is a worst-case misalignment of perceived bit time, the data samples rt8, rt9, and rt10 are within the bit time and data recovery is successful. figure 14-9. start bit search example 3 reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 0 1 111000 00 lsb 0 0 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt11 rt10 rt9 rt14 rt13 rt12 rt2 rt1 rt16 rt15 rt3 rt4 rt5 rt6 rt7 samples rt clock rt clock count actual start bit rxd 11 1 1 11000 0 lsb 0 0 perceived start bit reset rt clock rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt13 rt12 rt11 rt16 rt15 rt14 rt4 rt3 rt2 rt1 rt5 rt6 rt7 rt8 rt9 samples rt clock rt clock count actual start bit rxd 10 1 11000 0 lsb 0 perceived start bit functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 163 figure 14-10 shows the effect of noise early in the start bi t time. although this noise does not affect proper synchronization with the start bit time, it does set the noise flag. figure 14-10. start bit search example 4 figure 14-11 shows a burst of noise near the beginning of th e start bit that resets the rt clock. the sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag. figure 14-11. start bit search example 5 in figure 14-12 a noise burst makes the majority of data samples rt8, rt9, and rt10 high. this sets the noise flag but does not reset the rt clock. in start bits only, the rt8, rt9, and rt10 data samples are ignored. figure 14-12. start bit search example 6 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count perceived and actual start bit rxd 11 1 1100 1 lsb 1 1 1 1 reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 samples rt clock rt clock count start bit rxd 11 1 1101 0 lsb 1 1 1 1 1 00 0 00 0 0 0 no start bit found reset rt clock rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt7 rt6 rt5 rt10 rt9 rt8 rt14 rt13 rt12 rt11 rt15 rt16 rt1 rt2 rt3 samples rt clock rt clock count start bit rxd 11 1 1100 0 lsb 1 1 1 1 0 11 0 serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 164 freescale semiconductor 14.5.4.4 framing errors if the data recovery logic does not detect a logic 1 wh ere the stop bit should be in an incoming frame, it sets the framing error flag, fe, in sci status register 1 (scsr1). a break character also sets the fe flag because a break character has no stop bit. the fe flag is set at the same time that the rdrf flag is set. 14.5.4.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming frame, it resync hronizes the rt clock on any valid falling edge within the frame. resynchronization within frames corre cts misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 14-13 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 14-13. slow data for an 8-bit data character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 14-13 , the receiver counts 154 rt cycles at the point when the count of the transmitti ng device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent difference between the receiver c ount and the transmitter count of a slow 8-bit data character with no errors is: for a 9-bit data character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 14-13 , the receiver counts 170 rt cycles at the point when the count of the transmitti ng device is: 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------------------- - 100 4.54% = 170 163 ? 170 ------------------------- - 100 4.12% = functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 165 fast data tolerance figure 14-14 shows how much a fast received frame can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still sampled at rt8, rt9, and rt10. figure 14-14. fast data for an 8-bit data character, data sampling of the stop bit takes the receiver 9bittimes 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 14-14 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: for a 9-bit data character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 14-14 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is: 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: 14.5.4.6 receiver wakeup so that the sci can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting t he receiver wakeup bit, rwu, in sci control register 2 (sccr2) puts the receiver into a standby stat e during which receiver interrupts are disabled. the transmitting device can address messages to select ed receivers by including addressing information in the initial frame or frames of each message. the wake bit in sci control register 1 (sccr1) deter mines how the sci is brought out of the standby state to process an incoming message. the wake bit enables either idle line wakeup or address mark wakeup: idle input line wakeup (wake = 0) ? in this wakeup method, an idle condition on the rxd pin clears the rwu bit and wakes up the sci. the initial frame or frames of every message contain addressing information. all receivers evaluate the addressing information, and receivers for which idle or next frame stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------------------- - 100 3.90% = 170 176 ? 170 ------------------------- - 100 3.53% = serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 166 freescale semiconductor the message is addressed process the frames that follow. any receiver for which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another idle character appears on the rxd pin. idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. the idle character that wakes a receiver does not set the receiver idle flag, idle, or the receive data register full flag, rdrf. the idle line type bit, ilt, determines whether t he receiver begins counting logic 1s as idle character bits after the start bit or after the st op bit. ilt is in sci control register 1 (sccr1). address mark wakeup (wake = 1) ? in this wakeup method, a logic 1 in the most significant bit (msb) position of a frame clears the rwu bit and wakes up the sci. the logic 1 in the msb position marks a frame as an address frame that co ntains addressing information. all receivers evaluate the addressing information, and the re ceivers for which the message is addressed process the frames that follow. any receiver fo r which a message is not addressed can set its rwu bit and return to the standby state. the rwu bit remains set and the receiver remains on standby until another address frame appears on the rxd pin. the logic 1 msb of an address frame clears the rece iver?s rwu bit before the stop bit is received and sets the rdrf flag. address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle can cause the receiver to wake up immediately. 14.5.5 single-wi re operation normally, the sci uses two pins for transmitting and rece iving. in single-wire operation, the rxd pin is disconnected from the sci and is available as a genera l-purpose i/o pin. the sci uses the txd pin for both receiving and transmitting. setting the data direction bit for the txd pin configures txd as the output for transmitted data. clearing the data direction bit configures txd as the input for received data. figure 14-15. single-wire operation (loops = 1 and rsrc = 1) txd rxd transmitter receiver woms ddrs bit = 1 ddrs bit = 0 general- purpose i/o txd rxd transmitter receiver general- purpose i/o nc functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 167 enable single-wire operation by setting the loops bit and the receiver source bit, rsrc, in sci control register 1 (sccr1). setting the loops bit disables the path from the rxd pin to the receiver. setting the rsrc bit connects the receiver input to the output of the txd pin driver. both the transmitter and receiver must be enabled (te = 1 and re = 1). the wired-or mode select bit, woms, configures the tx d pin for full cmos drive or for open-drain drive. woms controls the txd pin in both normal operation and in single-wire operation. when woms is set, the data direction bit for the txd pin does not have to be cleared for txd to receive data. 14.5.6 loop operation in loop operation, the transmitter output goes to the re ceiver input. the rxd pin is disconnected from the sci and is available as a general-purpose i/o pin. setting the data direction bit for the txd pin connects the transmitter output to the txd pin. clearing the data direction bit disconnects the transmitter output from the txd pin. figure 14-16. loop operation (loop = 1 and rsrc = 0) enable loop operation by setting the loops bit and clearing the rsrc bit in sci control register 1 (sccr1). setting the loops bit disables the path fr om the rxd pin to the receiver. clearing the rsrc bit connects the transmitter output to the receiver input. both the transmitter and receiver must be enabled (te = 1 and re = 1). the wired-or mode select bit, woms, configures the tx d pin for full cmos drive or for open-drain drive. woms controls the txd pin in both normal operation and in loop operation. txd rxd woms ddrs bit = 1 ddrs bit = 0 general- purpose i/o txd rxd woms general- purpose i/o h transmitter receiver transmitter receiver serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 168 freescale semiconductor 14.6 register description s and reset initialization this section provides register descriptions and reset initialization. 14.6.1 sci baud rate registers read: anytime write: sbr[12:0] anytime; btst, bspl , and brld only in special modes btst ? reserved for test function bspl ? reserved for test function brld ? reserved for test function sbr[12:0] ? sci baud rate bits the value written to sbr[12:0] determines the baud rate of the sci. the new value takes effect when the low order byte is written. the formula for calculating baud rate is: br = value written to sbr[12:0], a value from 1 to 8191 note the baud rate generator is disabled until the te bit or the re bit is set for the first time after reset. the baud rate generator is disabled when br = 0. sci0: $00c0 sci1: $00c8 bit 7654321bit 0 read: btst bspl brld sbr12 sbr11 sbr10 sbr9 sbr8 write: reset:00000000 figure 14-17. sci baud rate register high (sc0bdh or sc1bdh) sci0: $00c1 sci1: $00c9 bit 7654321bit 0 read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: reset:00000100 figure 14-18. sci baud rate register low (sc0bdl or sc1bdl) sci baud rate mclk 16 br --------------------- = register descriptions and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 169 14.6.2 sci cont rol register 1 read: anytime write: anytime loops ? loop select bit loops enables loop operation. in loop operation the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use the loop function. 1 = loop operation enabled 0 = normal operation enabled the receiver input is determined by the rsrc bit. the transmitter output is controlled by the associated ddrs bit. if the data direction bit for the txd pin is set and loops = 1, the transmitter output appears on the txd pin. if the ddrs bit is clear and loops = 1, the txd pin is idle (high) if rsrc = 0 and high-impedance if rsrc = 1. see table 14-7 . woms ? wired-or mode select bit woms configures the txd and rxd pins for open-dr ain operation. woms allows txd pins to be tied together in a multiple-transmitter system. then the tx d pins of non-active transmitters follow the logic level of an active 1. woms also affects the txd and rxd pins when they are general-purpose outputs. external pullup resistors are necessary on open-drain outputs. 1 = txd and rxd pins, open-drain when outputs 0 = txd and rxd pins, full cmos drive capability rsrc ? receiver source bit when loops = 1, the rsrc bit determines the internal feedback path for the receiver. 1 = receiver input connected to txd pin 0 = receiver input internally connected to transmitter output sci0: $00c2 sci1: $00ca bit 7654321bit 0 read: loops woms rsrc m wake ilt pe pt write: reset:00000000 figure 14-19. sci control register 1 (sc0cr1 or sc1cr1) table 14-7. loop mode functions loops rsrc ddrsx (1) woms function of txd pin 0 x x x normal operation 10 0 x loop mode; transmitter output connected to receiver input txd pin disconnected 10 1 0 loop mode; transmitter output connected to receiver input txd is cmos output 10 1 1 loop mode; transmitter output connected to receiver input txd is open-drain output serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 170 freescale semiconductor m ? mode bit m determines whether data characters are eight or nine bits long. 1 = one start bit, nine data bits, one stop bit 0 = one start bit, eight data bits, one stop bit wake ? wakeup bit wake determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received data characte r or an idle condition on the rxd pin. 1 = address mark wakeup 0 = idle line wakeup ilt ? idle line type bit ilt determines when the receiver starts counting l ogic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if th e count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recogniti on, but requires properly synchronized transmissions. 1 = idle character bit count begins after stop bit. 0 = idle character bit count begins after start bit. pe ? parity enable bit pe enables the parity function. when enabled, the parity function inserts a parity bit in the most significant bit position. 1 = parity function enabled 0 = parity function disabled pt ? parity type bit pt determines whether the sci generates and checks for even parity or odd parity. with even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. with odd parity, an odd number of 1s clears the parity bit an d an even number of 1s sets the parity bit. 1 = odd parity 0 = even parity 11 0 x single-wire mode; transmitter output disconnected txd is high-impedance receiver input 1 1 1 0 single-wire mode; txd pin connected to receiver input 11 1 1 single wire mode; txd pin connected to receiver input txd is open-drain for receiving and transmitting 1. ddrsx means the data direction bit of the txd pin. table 14-7. loop mode functions (continued) loops rsrc ddrsx (1) woms function of txd pin register descriptions and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 171 14.6.3 sci cont rol register 2 read: anytime write: anytime tie ? transmitter interrupt enable bit tie enables the transmit data register empty flag, tdre, to generate interrupt requests. 1 = tdre interrupt requests enabled 0 = tdre interrupt requests disabled tcie ? transmission complete interrupt enable bit tcie enables the transmission complete flag, tc, to generate interrupt requests. 1 = tc interrupt requests enabled 0 = tc interrupt requests disabled rie ? receiver interrupt enable bit rie enables the receive data register full flag, rdrf, and the overrun flag, or, to generate interrupt requests. 1 = rdrf and or interrupt requests enabled 0 = rdrf and or interrupt requests disabled ilie ? idle line interrupt enable bit ilie enables the idle line flag, idle, to generate interrupt requests. 1 = idle interrupt requests enabled 0 = idle interrupt requests disabled te ? transmitter enable bit te enables the sci transmitter and configures the tx d pin as the sci transmitter output. the te bit can be used to queue an idle preamble. 1 = transmitter enabled 0 = transmitter disabled re ? receiver enable bit re enables the sci receiver. 1 = receiver enabled 0 = receiver disabled rwu ? receiver wakeup bit 1 = standby state 0 = normal operation rwu enables the wakeup function and inhibits further receiver interrupt requests. normally, hardware wakes the receiver by automatically clearing rwu. sci0: $00c3 sci1: $00cb bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000 figure 14-20. sci control register 2 (sc0cr2 or sc1cr2) serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 172 freescale semiconductor sbk ? send break bit toggling sbk sends one brea k character (10 or 11 logic 0s). as long as sbk is set, the transmitter sends logic 0s. 1 = transmit break characters 0 = no break characters 14.6.4 sci status register 1 read: anytime write: has no meaning or effect tdre ? transmit data register empty flag tdre is set when the transmit shift register receives a byte from the sci data register. clear tdre by reading sci status register 1 with tdre set and t hen writing to the low byte of the sci data register. 1 = transmit data register empty 0 = transmit date register not empty tc ? transmission complete flag tc is set when the tdre flag is set and no data, preamble, or break character is being transmitted. when tc is set, the txd pin becomes idle (logic 1). cl ear tc by reading sci status register 1 with tc set and then writing to the low byte of the sci data register. tc clears automatically when a break, preamble, or data is queued and ready to be sent. 1 = transmission complete 0 = transmission in progress rdrf ? receive data register full flag rdrf is set when the data in the receive shift regi ster transfers to the sci data register. clear rdrf by reading sci status register 1 with rdrf set and then reading the low byte of the sci data register. 1 = receive data register full 0 = data not available in sci data register idle ? idle line flag idle is set when 10 consecutive logic 1s (if m = 0) or 11 consecutive logic 1s (if m = 1) appear on the receiver input. clear idle by reading sci status r egister 1 with idle set and then writing to the low byte of the sci data register. once idle is clear ed, a valid frame must again set the rdrf flag before an idle condition can set the idle flag. 1 = receiver input has become idle 0 = receiver input is either active now or has never become active since the idle flag was last cleared note when the receiver wakeup bit (rwu) is set, an idle line condition does not set the idle flag. sci0: $00c4 sci1: $00cc bit 7654321bit 0 read: tdre tc rdrf idle or nf fe pf write: reset:11000000 = unimplemented figure 14-21. sci status register 1 (sc0sr1 or sc1sr1) register descriptions and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 173 or ? overrun flag or is set when software fails to read the sci data r egister before the receive shift register receives the next frame. the data in the shift register is lost, but the data already in the sci data registers is not affected. clear or by reading sci status register 1 with or set and then reading the low byte of the sci data register. 1 = overrun 0 = no overrun nf ? noise flag nf is set when the sci detects noise on the receiver input. nf is set during the same cycle as the rdrf flag but does not get set in the case of an ov errun. clear nf by reading sci status register 1 and then reading the low byte of the sci data register. 1 = noise 0 = no noise fe ? framing error flag fe is set when a logic 0 is accepted as the stop bi t. fe is set during the same cycle as the rdrf flag but does not get set in the case of an overrun. fe i nhibits further data reception until it is cleared. clear fe by reading sci status register 1 with fe set and then reading the low byte of the sci data register. 1 = framing error 0 = no framing error pf ? parity error flag pf is set when the parity enable bit, pe, is set and the parity of the received data does not match its parity bit. clear pf by reading sci status register 1 and then reading the low byte of the sci data register. 1 = parity error 0 = no parity error 14.6.5 sci status register 2 read: anytime write: has no meaning or effect raf ? receiver active flag raf is set when the receiver detects a logic 0 durin g the rt1 time period of the start bit search. raf is cleared when the receiver detects false start bits (usually from noise or baud rate mismatch) or when the receiver detects an idle character. 1 = reception in progress 0 = no reception in progress sci0: $00c5 sci1: $00cd bit 7654321bit 0 read:0000000raf write: reset:00000000 = unimplemented figure 14-22. sci status register 2 (sc0sr2 or sc1sr2) serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 174 freescale semiconductor 14.6.6 sci data registers read: anytime; reading accesses receive data register write: anytime; writing accesses transmit data register; writing to r8 has no effect r8 ? received bit 8 r8 is the ninth data bit received when the sci is configured for 9-bit data format (m = 1). t8 ? transmitted bit 8 t8 is the ninth data bit transmitted when the sci is configured for 9-bit data format (m = 1). r7?r0 ? received bits 7?0 t7?t0 ? transmitted bits 7?0 note if the value of t8 is the same as in the previous transmission, t8 does not have to be rewritten. the same value is transmitted until t8 is rewritten. in 8-bit data format, only sci dat a register low (scdrl) needs to be accessed. when transmitting in 9-bit data format and using 8-bit write instructions, write first to sci data register high (scdrh). sci0: $00c6 sci1: $00ce bit 7654321bit 0 read: r8 t8 000000 write: reset: unaffected by reset = unimplemented figure 14-23. sci data register high (sc0drh or sc1drh) sci0: $00c7 sci1: $00cf bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 14-24. sci data register low (sc0drl or sc1drl) external pin descriptions mc68hc812a4 data sheet, rev. 7 freescale semiconductor 175 14.7 external pin descriptions this section provides a description of tx d and rxd, the sci?s two external pins. 14.7.1 txd pin txd is the sci transmitter pin. txd is available fo r general-purpose i/o when it is not configured for transmitter operation. 14.7.2 rxd pin rxd is the sci receiver pin. rxd is available for gener al-purpose i/o when it is not configured for receiver operation. 14.8 modes of operation the sci functions the same in norma l, special, and emulation modes. 14.9 low-power options this section provides a description of the three low-power modes: run mode wait mode stop mode 14.9.1 run mode clearing the transmitter enable or receiver enable bi ts (te or re) in sci control register 2 (sccr2) reduces power consumption in run mode. sci registers are still accessible when te or re is cleared, but clocks to the core of the sci are disabled. 14.9.2 wait mode the sci remains active in wait mode. any enabled interrupt request from the sci can bring the mcu out of wait mode. if sci functions are not required during wait mode, r educe power consumption by disabling the sci before executing the wait instruction. 14.9.3 stop mode for reduced power consumption, the sci is inactive in stop mode. the stop instruction does not affect sci register states. sci operation resumes after an external interrupt. exiting stop mode by reset aborts any transmission or reception in progress and resets the sci. serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 176 freescale semiconductor 14.10 interrupt sources 14.11 general-purpose i/o ports port s shares its pins with the multiple serial in terface (msi). in all modes , port s pins ps7?ps0 are available for either general-purpose i/o or for sci and spi functions. see chapter 13 multiple serial interface (msi) . 14.12 serial character tr ansmission using the sci code is intended to use sci1 to serially transmit characters usi ng polling to the lcd display on the udlp1 board: when the transmission data register is empty a flag will get set, which is telling us that sc1dr is ready so we can write another byte. the transmission is performed at a baud rate of 9600. since the sci1 is only being used for transmit data, the data register wi ll not be used bidirectionally for received data. 14.12.1 equipment for this exercise, use the m68hc812a4evb emulation board. table 14-8. sci interrupt sources interrupt source flag local enable ccr mask vector address sci0 sci1 transmit data register empty tdre tie i bit $ffd6, $ffd7 $ffd4, $ffd5 transmission complete tc tcie i bit receive data register full rdrf rie i bit receiver overrun or receiver idle idle ilie i bit serial character transmission using the sci mc68hc812a4 data sheet, rev. 7 freescale semiconductor 177 14.12.2 code listing note a comment line is delimited by a semicolon. if there is no code before comment, a semicolon ( ;) must be placed in the first column to avoid assembly errors. include 'equates.asm' ; equates for registers ; user variables ; bit equates ; ---------------------------------------------------------------------- ; main program ; ---------------------------------------------------------------------- org $7000 ; 16k on-board ram, user code data area, ; ; start main program at $4000 main: bsr init ; subroutine to initialize sci0 registers bsr trans ; subroutine to start transmission done: bra done ; always branch to done, convenient for breakpoint ; ---------------------------------------------------------------------- ; subroutine init: ; ---------------------------------------------------------------------- init: tpa ; transfer ccr to a accumulator oraa #$10 ; ored a with #$10 to set i bit tap ; transfer a to ccr movb #$34,sc1bdl ; set baud =9600, in sci1 baud rate reg. movb #$00,sc1cr1 ; initialize for 8-bit data format, ; ; loop mode and parity disabled,(sc1cr1) movb #$08,sc1cr2 ; set for no ints, and transmitter enabled(sc1cr2) ldaa sc1sr1 ; 1st step to clear tdre flag: read sc1sr1 std sc1drh ; 2nd step to clear tdre flag: write sc1dr register ldx #data ; use x as a pointer to data. rts ; return from subroutine ; ---------------------------------------------------------------------- ; transmit subroutine ; ---------------------------------------------------------------------- trans: brclr sc1sr1,#$80, trans ; wait for tdre flag movb 1,x+,sc1drl ; transmit character, increment x pointer cpx #eot ; detect if last character has been transmitted bne trans ; if last char. not equal to "eot", branch to trans rts ; else transmission complete, return from subroutine ; ---------------------------------------------------------------------- ; table : data to be transmitted ; ---------------------------------------------------------------------- data: dc.b 'freescale hc12 banner - june, 1999' dc.b $0d,$0a ; return (cr) ,line feed (lf) dc.b 'scottsdale, arizona' dc.b $0d,$0a ; return (cr) ,line feed (lf) eot: dc.b $04 ; byte used to test end of data = eot end ; end of program serial communications in terface modu le (sci) mc68hc812a4 data sheet, rev. 7 178 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 179 chapter 15 serial peripheral interface (spi) 15.1 introduction the serial peripheral interface (spi) allows fu ll-duplex, synchronous, seri al communications with peripheral devices. 15.2 features features of the spi include: full-duplex operation master mode and slave mode programmable slave-select output option programmable bidirectional data pin option two flags with interrupt-generation capability: ? transmission complete ? mode fault write collision detection read data buffer serial clock with programmable polarity and phase reduced drive control for lower power consumption programmable open-drain output option serial peripheral interface (spi) mc68hc812a4 data sheet, rev. 7 180 freescale semiconductor 15.3 block diagram figure 15-1. spi block diagram mosi or momi miso or siso sck ss interrupt baud rate divider clock clock logic cpha cpol spi lsbf ssoe swom modf wcol spif spc0 rds spe mstr control pups spr0 spr2 spr1 p-clock shift register port s data direction register port s data register 7 spie mstr request 654 shift control logic spi data register (write) spi data register (read) select pin control logic register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 181 15.4 register map note the register block can be mapped to any 2-kbyte boundary within the standard 64-kbyte address space. the r egister block occupies the first 512 bytes of the 2-kbyte block. this register map shows default addressing after reset. addr.register name bit 7654321bit 0 $00d0 spi 0 control register 1 (sp0cr1) see page 186. read: spie spe swom mstr cpol cpha ssoe lsbf write: reset:00000100 $00d1 spi 0 control register 2 (sp0cr2) see page 187. read:0000 pups rds 0 spc0 write: reset:00001000 $00d2 spi baud rate register (sp0br) see page 188. read:00000 spr2 spr1 spr0 write: reset:00000000 $00d3 spi status register (sp0sr) see page 189. read:spifwcol0modf0000 write: reset:00000000 $00d5 spi data register (sp0dr) see page 190. read: bit 76543210 write: reset: unaffected by reset $00d6 port s data register (ports) see page 147. read: ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 write: reset: unaffected by reset $00d7 port s data direction register (ddrs) see page 148. read: ddrs7 ddrs6 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 write: reset:00000000 = unimplemented figure 15-2. spi register map serial peripheral interface (spi) mc68hc812a4 data sheet, rev. 7 182 freescale semiconductor 15.5 functional description the spi allows full-duplex, sync hronous, serial communication betw een the mcu and peripheral devices, including other mcus. in master mode, the spi generates the synchronizing clock and initiates transmissions. in slave mode, the spi depends on a master peripheral to start and synchronize transmissions. 15.5.1 master mode the spi operates in master mode when the master mode bit, mstr, is set. note configure spi modules as master or slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. only a master spi module can initia te transmissions. begin the transm ission from a master spi module by writing to the spi data register. if the shift register is empty, the byte immediately transfers to the shift register. the byte begins shifting out on the master out, slave in pin (mosi) under the control of the serial clock. see figure 15-3 . as the byte shifts out on the mosi pin, a byte shifts in from the slave on the master in, slave out pin (miso) pin. on the eighth serial clock cycle, the transmissio n ends and sets the spi flag, spif. at the same time that spif becomes set, the byte from the slave transfers from the shift register to the spi data register. the byte remains in a read buffer until replaced by the next byte from the slave. figure 15-3. full-duplex master/slave connections 15.5.2 slave mode the spi operates in slave mode when mstr is clear. in slave mode, the sck pin is the input for the serial clock from the master. note before a transmission occurs, the ss pin of the slave spi must be at logic 0. the slave ss pin must remain low until the transmission is complete. a transmission begins when initiated by a master spi. the byte from the master spi begins shifting in on the slave mosi pin under the control of the master serial clock. as the byte shifts in on the mosi pi n, a byte shifts out on the miso pin to the master shift register. on the eighth serial clock cycle, the transmission ends and sets the spi fl ag, spif. at the same time that spif shift register shift register clock divider master mcu slave mcu v dd mosi mosi miso miso sck sck ss ss functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 183 becomes set, the byte from the master transfers to the spi data register. the byte remains in a read buffer until replaced by the next byte from the master. 15.5.3 baud rate generation a clock divider in the spi produces eight divided p-clock signals. the p-clock divisors are 2, 4, 8, 16, 32, 64, 128, and 256. the spr[2:1:0] bits select one of the divided p-clock signals to control the rate of the shift register. through the sck pin, the selected clock signa l also controls the rate of the shift register of the slave spi or other slave peripheral. the clock divider is active only in master mode and only when a transmission is taking place. otherwise, the divider is disabled to save power. 15.5.4 clock phase and polarity the clock phase and clock polarity bits, cpha and cpol, can select any of four combinations of serial clock phase and polarity. the cpha bit determines whether a falling ss edge or the first sck edge begins the transmission. the cpol bit determines wh ether sck is active-high or active-low. note to transmit between spi modules, both modules must have identical cpha and cpol values. when cpha = 0, a falling ss edge signals the slave to begin transmi ssion. the capture strobe for the first bit occurs on the first serial clock edge. theref ore, the slave must begin driving its data before the first serial clock edge. after transmis sion of all eight bits, the slave ss pin must toggle from low to high to low again to begin another transmission. this format may be preferable in systems having more than one slave driving the master miso line. figure 15-4. transmission format 0 (cpha = 0) sck sck mosi miso ss capture strobe to slave cpol = 0 cpol = 1 end from master from slave sck cycles 1 2 3 4 5 6 7 8 t t t i t l begin transfer transfer msb first (lsbf = 0) lsb first (lsbf = 1) msbbit 6bit 5bit 4bit 3bit 2bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb minimum t l , t t , and t i = 1/2 sck cycle serial peripheral interface (spi) mc68hc812a4 data sheet, rev. 7 184 freescale semiconductor figure 15-5. slave ss toggling when cpha = 0 when cpha = 1, the master begins driving its mosi pin and the slave begins driving its miso pin on the first serial clock edge. the ss pin can remain low between transmissions. this format may be preferable in systems having only one slave driving the master miso line. note the slave sck pin must be in the proper idle state before the slave is enabled. figure 15-6. transmission format 1 (cpha = 1) figure 15-7. slave ss when cpha = 1 byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 sck sck mosi miso ss capture strobe to slave cpol = 0 cpol = 1 end from master from slave sck cycles 1 2 3 4 5 6 7 8 t t t i t l begin transfer transfer msb first (lsbf = 0) lsb first (lsbf = 1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb minimum t l , t t , and t i = 1/2 sck cycle byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 1 functional description mc68hc812a4 data sheet, rev. 7 freescale semiconductor 185 15.5.5 ss output in master mode only, the ss pin can function as a chip-select output for connection to the ss input of a slave. the master ss output automatically selects the slav e by going low for eac h transmission and deselects the slave by going high during each idling state. enable the ss output by setting the master mode bit, mstr , the slave-select output enable bit, ssoe, and the data direction bit of the ss pin. mstr and ssoe are in spi control register 1. 15.5.6 single-wi re operation normally, the spi operates as a 2-wire interface; it uses its mosi and miso pins for transmitting and receiving. in single-wire operation, a master spi uses the mosi pin for both receiving and transmitting. the mosi pin becomes a master out, master in (momi) pin. the miso pin is disconnected from the spi and is available as a general-purpose port s i/o pin. a slave spi in single-wire operation uses the miso pin for both receiving and transmitting. the miso pin becomes a slave in, slave out (siso) pin. the mosi pin is disconnected from the spi and is available as a general-purpose i/o pin. setting serial pin control bit 0, spc 0, configures the spi for single-w ire operation. the direction of the single-wire pin depends on its data direction bit. figure 15-8. single-wire operation (spc0 = 1) table 15-1. ss pin configurations control bits ss pin function ddrs7 ssoe master mode slave mode 0 0 slave-select input with mode-fault detection slave-select input 01 reserved 1 0 general-purpose output 1 1 slave-select output spi momi ps4 serial out serial in ddrs5 spi ps5 siso ddrs4 serial in serial out master mode slave mode general- purpose i/o general- purpose i/o serial peripheral interface (spi) mc68hc812a4 data sheet, rev. 7 186 freescale semiconductor 15.6 spi register descript ions and reset initialization this section describes the spi registers and reset initialization. 15.6.1 spi cont rol register 1 read: anytime write: anytime spie ? spi interrupt enable bit spie enables the spif and modf flags to generate interrupt requests. 1 = spif and modf interrupt requests enabled 0 = spif and modf interrupt requests disabled spe ? spi enable bit setting the spe bit enables the sp i and configures port s pins 7 ?4 for spi functions. clearing spe puts the spi in a disabled, low-power state. 1 = spi enabled 0 = spi disabled note when the modf flag is set, spe always reads as logic 0. writing to spi control register 1 is part of the mode fault recovery sequence. swom ? port s wired-or mode bit swom disables the pullup devices on port s pins 7?4 so that they become open-drain outputs. 1 = open-drain port s pin 7?4 outputs 0 = normal push-pull port s pin 7?4 outputs mstr ? master mode bit mstr selects master mode operation or slave mode operation. 1 = master mode 0 = slave mode cpol ? clock polarity bit cpol determines the logic state of the se rial clock pin between transmissions. see figure 15-4 and figure 15-6 . 1 = active-high sck 0 = active-low sck cpha ? clock phase bit cpha determines whether transmission be gins on the falling edge of the ss pin or on the first edge of the serial clock. see figure 15-4 and figure 15-6 . 1 = transmission at first sck edge 0 = transmission at falling ss edge address: $00d0 bit 7654321bit 0 read: spie spe swom mstr cpol cpha ssoe lsbf write: reset:00000100 figure 15-9. spi control register 1 (sp0cr1) spi register descriptions and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 187 ssoe ? slave select output enable bit ssoe enables the output function of master ss pin when the ddrs7 bit is also set. 1 = ss output enabled 0 = ss output disabled lsbf ? lsb first bit lsbf enables least-significant-bit-fir st transmissions. it does not affect the position of data in the spi data register; reads and writes of the spi data register always have the msb in bit 7. 1 = least-significant-bit-first transmission 0 = most-significant-bit-first transmission 15.6.2 spi cont rol register 2 read: anytime write: anytime pups ? pullup port s bit setting pups enables internal pullup devices on all port s input pins. if a pin is programmed as output, the pullup device becomes inactive. 1 = pullups enabled 0 = pullups disabled rds ? reduced drive port s bit setting rds lowers the drive capability of all port s output pins for lower power consumption and less noise. 1 = reduced drive 0 = normal drive spc0 ? serial pin control bit 0 spc0 enables single-wire operation of the mosi and miso pins. address: $00d1 bit 7654321bit 0 read:0000 pups rds 0 spc0 write: reset:00001000 = unimplemented figure 15-10. spi control register 2 (sp0cr2) table 15-2. single-wire operation control bits pins spc0 mstr ddrs5 ddrs4 mosi miso 1 1 0 1 ? master input master output general-purpose i/o 0? 0 1 general-purpose i/o slave input slave output serial peripheral interface (spi) mc68hc812a4 data sheet, rev. 7 188 freescale semiconductor 15.6.3 spi baud rate register read: anytime write: anytime spr2?spr0 ? spi clock rate select bits these bits select one of eight spi baud rates as shown in table 15-3 . reset clears spr2?spr0, selecting e-clock divided by two. address: $00d2 bit 7654321bit 0 read:00000 spr2 spr1 spr0 write: reset:00000000 = unimplemented figure 15-11. spi baud rate register (sp0br) table 15-3. spi clock rate selection spr[2:1:0] e-clock divisor baud rate (e-clock = 4 mhz) baud rate (e-clock = 8 mhz) 000 2 2.0 mhz 4.0 mhz 001 4 1.0 mhz 2.0 mhz 010 8 500 khz 1.0 mhz 011 16 250 khz 500 khz 100 32 125 khz 250 khz 101 64 62.5 khz 125 khz 110 128 31.3 khz 62.5 khz 111 256 15.6 khz 31.3 khz spi register descriptions and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 189 15.6.4 spi status register read: anytime write: has no meaning or effect spif ? spi flag spif is set after the eighth serial clock cycle of a transmissson. spif generates an interrupt request if the spie bit in spi control register 1 is set also. cl ear spif by reading the spi status register with spif set and then reading or writing to the spi data register. 1 = transfer complete 0 = transfer not complete wcol ? write collision flag wcol is set when a write to the spi data register occurs during a data transfer. the byte being transferred continues to shift out of the shift register, and the data written during the transfer is lost. wcol does not generate an interrupt request. wcol can be read when the transfer in progress is complete. clear wcol by reading the spi status register with wcol set and then reading or writing to the spi data register. 1 = write collision 0 = no write collision modf ? mode fault flag modf is set if the ps7 pin goes to l ogic 0 when it is configured as the ss input of a master spi (mstr = 1 and ddr7 = 0). clear modf by reading the spi status register with modf set and then writing to spi control register 1. 1 = mode fault 0 = no mode fault note modf is inhibited when the ps7 pin is configured as: the ss output, ddrs7 = 1 and ssoe = 1, or a general-purpose output, ddrs7 = 1 and ssoe = 0 address: $00d3 bit 7654321bit 0 read:spifwcol0modf0000 write: reset:00000000 = unimplemented figure 15-12. spi status register (sp0sr) serial peripheral interface (spi) mc68hc812a4 data sheet, rev. 7 190 freescale semiconductor 15.6.5 spi data register read: anytime; normally, only after spif flag set write: anytime a data transfer is not taking place the spi data register is both the input and output register for spi data. reads are double-buffered but writes cause data to be written directly into the spi shift register. the data registers of two spis can be connected through their mosi and miso pins to form a distributed 16-bit register. a transmission between the spis shifts the data eight bit positions, exc hanging the data between the master and the slave. the slave can also be another simpler device that only re ceives data from the master or that only sends data to the master. 15.7 external pins the spi module has four i/o pins: miso ? master data in, slave data out mosi ? master data out, slave data in sck ? serial clock ss ? slave select the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becom es an open-drain output when the swom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 15.7.1 miso (master in, slave out) in a master spi, miso is the data input. in a slave spi, miso is the data output. in a slave spi, the miso output pin is enabled only when its ss pin is at logic 0. to support a multiple-slave system, a logic 1 on the ss pin of a slave puts the miso pin in a high-impedance state. 15.7.2 mosi (mas ter out, slave in) in a master spi, mosi is the data output. in a slave spi, mosi is the data input. 15.7.3 sck (serial clock) the serial clock synchronizes data transmission betw een master and slave devices. in a master spi, the sck pin is the clock output to the slave. in a slave mcu, the sck pin is the clock input from the master. address: $00d5 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: unaffected by reset figure 15-13. spi data register (sp0dr) low-power options mc68hc812a4 data sheet, rev. 7 freescale semiconductor 191 15.7.4 ss (slave select) the ss pin has multiple functions that depend on spi configuration: the ss pin of a slave spi is always configured as an input and allows the slave to be selected for transmission. when the cpha bit is clear, the ss pin signals the start of a transmission. the ss pin of a master spi can be configured as a mode-fault input, a slave-select output, or a general-purpose output. ? as a mode-fault input (mstr = 1, ddrs7 = 0, ssoe = 0), the ss pin can detect multiple masters driving mosi and spsck. ? as a slave-select output (mstr = 1, ddrs7 = 1, ssoe = 1), the ss pin can select slaves for transmission. ? when mstr = 1, ddrs7 = 1, and ssoe = 0, the ss pin is available as a general-purpose output. 15.8 low-power options this section describes the three low-power modes: run mode wait mode stop mode 15.8.1 run mode clearing the spi enable bit, spe, in spi control regist er 1 reduces power consumption in run mode. spi registers are still accessible when spe is cleared, but clocks to the core of the spi are disabled. 15.8.2 wait mode the spi remains active in wait mode. any enabled interrupt request from the spi can bring the mcu out of wait mode. if spi functions are not required during wait mode, reduce power consumption by disabling the spi before executing the wait instruction. 15.8.3 stop mode for reduced power consumption, the spi is inactive in stop mode. the stop instruction does not affect spi register states. spi operation resumes after an external interrupt. exiting stop mode by reset aborts any transmission in progress and rese ts the spi. entering stop mode during a transmission results in invalid data. serial peripheral interface (spi) mc68hc812a4 data sheet, rev. 7 192 freescale semiconductor 15.9 interrupt sources 15.10 general-purpose i/o ports port s shares its pins with the multiple serial in terface (msi). in all modes , port s pins ps7?ps0 are available for either general-purpose i/o or for sci and spi functions. see chapter 13 multiple serial interface (msi) . 15.11 synchronous character transmission using the spi this program is intended to communicate with the hc11 on the udlp1 board. it utilizes the spi to transmit synchronously characters in a string to be displayed on the lcd display. the program must configure the spi as a master, and non-interrupt driv en. the slave peripheral is chip-selected with the ss line at low voltage level. between 8 bit transfers the ss line is held high. also the clock idles low and takes data on the rising clock edges. the serial clock is set not to exceed 100 khz baud rate. 15.11.1 equipment for this exercise, use the m68hc812a4evb emulation board. 15.11.2 code listing note a comment line is delimited by a semicolon. if there is no code before comment, a semicolon ( ;) must be placed in the first column to avoid assembly errors. include 'equates.asm' ;equates for all registers ; user variables ; bit equates ; ---------------------------------------------------------------------- ; main program ; ---------------------------------------------------------------------- org $7000 ; 16k on-board ram, user code data area, ; ; start main program at $7000 main: bsr init ; subroutine to initialize spi registers bsr transmit ; subroutine to start transmission finish: bra finis ; finished transmitting all data table 15-4. spi interrupt sources interrupt source flag local enable ccr mask vector address transmission complete spif spie i bit $ffd8, $ffd9 mode fault modf synchronous character tran smission using the spi mc68hc812a4 data sheet, rev. 7 freescale semiconductor 193 ; ---------------------------------------------------------------------- ;* subroutine init: ; ---------------------------------------------------------------------- init: bset ports,#$80 ; set ss line high to prevent glitch movb #$e0,ddrs ; configure port s input/ouput levels ; ; mosi, sck, ss* = ouput, miso=input movb #$07,sp0br ; select serial clock baud rate < 100 khz movb #$12,sp0cr1 ; configure spi(sp0cr1): no spi interrupts, ; ; mstr=1, cpol=0, cpha=0 movb #$08,sp0cr2 ; config. ports output drivers to operate normally, ; ; and with active pull-up devices. ldx #data ; use x register as pointer to first character ldaa sp0sr ; 1st step to clear spif flag, read sp0sr ldaa sp0dr ; 2nd step to clear spif flag, access sp0dr bset sp0cr1,#$40 ; enable the spi (spe=1) rts ; return from subroutine ; ---------------------------------------------------------------------- ;* transmit subroutine ; ---------------------------------------------------------------------- transmit: ldaa 1,x+ ; load acc. with "new" character to send, inc x beq done ; detect if last character(0) has been transmitted ; ; if last char. branch to done, else bclr ports,#$80 ; assert ss line to start x-misssion. staa sp0dr ; load data into data reg.,x-mit. ; ; it is also the 2nd step to clear spif flag. flag: brclr sp0sr,#$80,flag ;wait for flag. bset ports,#$80 ; disassert ss line. bra transmit ; continue sending characters, branch to transmit. done: rts ; return from subroutine ; ---------------------------------------------------------------------- ; table of data to be transmitted ; ---------------------------------------------------------------------- data: dc.b 'freescale' dc.b $0d,$0a ; return (cr) ,line feed (lf) eot: dc.b $00 ; byte used to test end of data = eot end ; end of program serial peripheral interface (spi) mc68hc812a4 data sheet, rev. 7 194 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 195 chapter 16 analog-to-digital converter (atd) 16.1 introduction the analog-to-digital converter (atd) is an 8-channel, 8-bit, multiplexed-input, successive approximation analog-to-digital converter, accurate to 1 least significant bit (lsb). it do es not require external sample and hold circuits because of the type of charge redi stribution technique used. the atd converter timing can be synchronized to the system p-clock. th e atd module consists of a 16-word (32-byte) memory-mapped control register block used for control, testing, and configuration. 16.2 features features of the atd module include: eight multiplexed input channels multiplexed-input succ essive approximation 8-bit resolution single or continuous conversion conversion complete flag with cpu interrupt request selectable atd clock analog-to-digital converter (atd) mc68hc812a4 data sheet, rev. 7 196 freescale semiconductor 16.3 block diagram figure 16-1. atd block diagram channel 0 sar rc dac array and comparator v dda v ssa v rl v rh analog mux and sample buffer amp an7/pad7 an6/pad6 an5/pad5 an4/pad4 an3/pad3 an2/pad2 an1/pad1 an0/pad0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 mode and timing control clock select/prescale port ad data input register register map mc68hc812a4 data sheet, rev. 7 freescale semiconductor 197 16.4 register map note the register block can be mapped to any 2-kbyte boundary within the standard 64-kbyte address space. the r egister block occupies the first 512 bytes of the 2-kbyte block. this register map shows default addressing after reset. addr.register name bit 7654321bit 0 $0060 atd control register 0 (atdctl0) see page 199. read: 00000000 write: reset:00000000 $0061 atd control register 1 (atdctl1) see page 199. read: 0 0 0 00000 write: reset:00000000 $0062 atd control register 2 (atdctl2) see page 200. read: adpu affc awai 000 ascie ascif write: reset:00000000 $0063 atd control register 3 (atdctl3) see page 201. read: 0 0 0 0 0 0 frz1 frz0 write: reset:00000000 $0064 atd control register 4 (atdctl4) see page 201. read: 0 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: reset:00000001 $0065 atd control register 5 (atdctl5) see page 202. read: 0 s8cm scan mult cd cc cb ca write: reset:00000000 $0066 atd status register 1 (atdstat1) see page 204. read: scf 0 0 0 0 cc2 cc1 cc0 write: reset:00000000 $0067 atd status register 2 (atdstat2) see page 204. read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: reset:00000000 $0068 atd test register 1 (atdtest1) see page 205. read: sar9 sar8 sar7 sar6 sar5 sar4 sar3 sar2 write: reset:00000000 $0069 atd test register 2 (atdtest2) see page 205. read: sar1 sar0 rst tstout tst3 tst2 tst1 tst0 write: reset:00000000 = unimplemented figure 16-2. atd i/o register summary analog-to-digital converter (atd) mc68hc812a4 data sheet, rev. 7 198 freescale semiconductor 16.5 functional description a single conversion sequence consists of four or ei ght conversions, depending on the state of the select 8-channel mode bit, s8cm, in atd control register 5 (atdctl5). there are eight basic conversion modes. in the non-scan modes, the sequence complete flag, sc f, is set after the sequence of four or eight conversions has been performed and the atd module halts. in the scan modes, the scf flag is set after the first sequence of four or eight conversions has been performed, and the atd module continues to restart the sequence. $006f port ad data input register (portad) see page 207. read: pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 write: reset:00000000 $0070 atd result register 0 (adr0h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $0072 atd result register 1 (adr1h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $0074 atd result register 2 (adr2h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $0076 atd result register 3 (adr3h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $0078 atd result register 4 (adr4h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $007a atd result register 5 (adr5h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $007c atd result register 6 (adr6h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate $007e atd result register 7 (adr7h) see page 206. read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate addr.register name bit 7654321bit 0 = unimplemented figure 16-2. atd i/o register summary (continued) registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 199 in both modes, the ccf flag associated with each regist er is set when that register is loaded with the appropriate conversion result. that flag is cleared aut omatically when that result register is read. the conversions are started by writing to the control registers. the atd control register 4 selects the clock source and sets up the prescaler. writes to the atd control registers initiate a new conversion sequence. if a write occurs while a conversion is in progress, the conversion is aborted and atd activity halts until a write to atdctl5 occurs. the atd control register 5 selects conversi on modes and conversion c hannel(s) and initiates conversions. a write to atdctl5 initiates a new conversion sequenc e. if a conversion sequence is in progress when a write occurs, the sequence is aborted and the scf and ccf flags are cleared. 16.6 registers and reset initialization this section describes the registers and reset initialization. 16.6.1 atd cont rol register 0 note writing to this register aborts the current conversion sequence. 16.6.2 atd cont rol register 1 address: $0060 bit 7654321bit 0 read: 00000000 write: reset:00000000 figure 16-3. atd control register 0 (atdctl0) address: $0061 bit 7654321bit 0 read:00000000 write: reset:00000000 = unimplemented figure 16-4. atd control register 1 (atdctl1) analog-to-digital converter (atd) mc68hc812a4 data sheet, rev. 7 200 freescale semiconductor 16.6.3 atd cont rol register 2 read: anytime write: anytime except ascif flag, which is read-only note writing to this register aborts the current conversion sequence. adpu ? atd power-up bit adpu enables the clock signal to the atd and powers up its analog circuits. 1 = atd enabled 0 = atd disabled note after adpu is set, the atd requires an analog circuit stabilization period. affc ? atd fast flag clear bit when affc is set, writing to a result register (a dr0h?adr7h) clears the associated ccf flag if it is set. when affc is clear, clearing a ccf flag requires a read of the status register followed by a read of the result register. 1 = fast ccf clearing enabled 0 = fast ccf clearing disabled awai ? atd stop in wait mode bit aswai disables the atd in wait mode for lower power consumption. 1 = atd disabled in wait mode 0 = atd enabled in wait mode ascie ? atd sequence complete interrupt enable bit ascie enables interrupt requests generated by the atd sequence complete interrupt flag, ascif. 1 = ascif interrupt requests enabled 0 = ascif interrupt requests disabled ascif ? atd sequence complete interrupt flag ascif is set when a conversion sequence is finished. if the atd sequence complete interrupt enable bit, ascie, is also set, ascif generates an interrupt request. 1 = conversion sequence complete 0 = conversion sequence not complete note the ascif flag is set only when a conversion sequence is completed and ascie = 1 or interrupts on the analog-to-digital converter (atd) module are enabled. address: $0062 bit 7654321bit 0 read: adpu affc awai 000 ascie ascif write: reset:00000000 = unimplemented figure 16-5. atd control register 2 (atdctl2) registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 201 16.6.4 adt cont rol register 3 frz1 and frz0 ? freeze bits the frz bits suspend atd operation for backg round debugging. when debugging an application, it is useful in many cases to have the atd pause when a breakpoint is encountered. these two bits determine how the atd responds when back ground debug mode becomes active. see table 16-1 . 16.6.5 atd cont rol register 4 smp1 and smp0 ? sample time select bits these bits select one of four sample times after the buffered sample and transfer has occurred. total conversion time depends on initial sample time (two atd clocks), transfer time (four atd clocks), final sample time (programmable, refer to table 16-2 ), and resolution time (10 atd clocks). address: $0063 bit 7654321bit 0 read:000000 frz1 frz0 write: reset:00000000 = unimplemented figure 16-6. atd control register 3 (atdctl3) table 16-1. atd response to background debug enable frz1:frz0 atd response 00 continue conversions in active background mode 01 reserved 10 finish current conversion, then freeze 11 freeze when bdm is active address: $0064 bit 7654321bit 0 read: 0 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: reset:00000001 = unimplemented figure 16-7. atd control register 4 (atdctl4) table 16-2. final sample time selection smp[1:0] final sample time to tal 8-bit conversion time 00 2 atd clock periods 18 atd clock periods 01 4 atd clock periods 20 atd clock periods 10 8 atd clock periods 24 atd clock periods 11 16 atd clock periods 32 atd clock periods analog-to-digital converter (atd) mc68hc812a4 data sheet, rev. 7 202 freescale semiconductor prs[4:0] ? prescaler select bits the prescaler divides the p-clock by the binary value written to prs[4:0] plus one. to assure symmetry of the prescaler output, an additional divide-by-two circuit generates the atd module clock. clearing prs[4:0] means the p-clock is di vided only by the di vide-by-two circuit. the reset state of prs[4:0] is 00001, giving a total p-clock divisor of four, which is appropriate for nominal operation at 2 mhz. table 16-3 shows the appropriate range of system clock frequencies for each p clock divisor. 16.6.6 atd cont rol register 5 read: anytime write: anytime s8cm ? select eight conversions mode bit s8cm selects conversion sequences of either eight or four conversions. 1 = eight conversion sequences 0 = four conversion sequences scan ? continuous channel scan bit scan selects a single conversion seq uence or continuous c onversion sequences. 1 = continuous conversion sequences (scan mode) 0 = single conversion sequence table 16-3. clock prescaler values prs[4:0] p-clock divisor max p-clock (1) 1. maximum conversion frequency is 2 mh z. maximum p-clock divisor value becomes maximum conversion rate that can be used on this atd module. min p-clock (2) 2. minimum conversion frequency is 500 khz. minimum p-clock divisor value becomes minimum conversion rate that this atd can perform. 00000 2 4 mhz 1 mhz 00001 4 8 mhz 2 mhz 00010 6 8 mhz 3 mhz 00011 8 8 mhz 4 mhz 00100 10 8 mhz 5 mhz 00101 12 8 mhz 6 mhz 00110 14 8 mhz 7 mhz 00111 16 8 mhz 8 mhz 01xxx do not use 1xxxx address: $0065 bit 7654321bit 0 read: 0 s8cm scan mult cd cc cb ca write: reset:00000000 = unimplemented figure 16-8. atd control register 5 (atdctl5) registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 203 mult ? multichannel conversion bit refer to table 16-4 . 1 = conversions of sequential channels 0 = conversions of a single input channel selected by the cd, cc, cb, and ca bits cd, cc, cb, and ca ? channel select bits the channel select bits select the input to convert. lt = 1, the atd sequencer selects table 16-4. multichannel mode result register assignment (1) 1. when mult = 1, bits with asterisks are do n?t care bits. the 4-conversion sequence from an0 to an3 or the 8-conversion sequence fr om an0 to an7 is completed in the order shown. when mult = 0, the cd, cc, cb, and ca bits select one input channel. the conversion sequence is performed on this channel only. s8cm cd cc cb ca channel input result in adrxh 00 0 0* 0* an0 adrxh0 0* 1* an1 adrxh1 1* 0* an2 adrxh2 1* 1* an3 adrxh3 1 0* 0* an4 adrxh0 0* 1* an5 adrxh1 1* 0* an6 adrxh2 1* 1* an7 adrxh3 01 0 0* 0* reserved adrxh0 0* 1* reserved adrxh1 1* 0* reserved adrxh2 1* 1* reserved adrxh3 1 0* 0* v rh adrxh0 0* 1* v rl adrxh1 1* 0* (v rh + v rl )/2 adrxh2 1* 1* test/reserved adrxh3 10 0* 0* 0* an0 adrxh0 0* 1* an1 adrxh1 1* 0* an2 adrxh2 1* 1* an3 adrxh3 1* 0* 0* an4 adrxh4 0* 1* an5 adrxh5 1* 0* an6 adrxh6 1* 1* an7 adrxh7 11 0* 0* 0* reserved adrxh0 0* 1* reserved adrxh1 1* 0* reserved adrxh2 1* 1* reserved adrxh3 1* 0* 0* v rh adrxh4 0* 1* v rl adrxh5 1* 0* (v rh + v rl )/2 adrxh6 1* 1* test/reserved adrxh7 analog-to-digital converter (atd) mc68hc812a4 data sheet, rev. 7 204 freescale semiconductor 16.6.7 atd status registers read: anytime write: special mode only scf ? sequence complete flag in single conversion sequence mode (scan = 0 in at dctl5), scf is set at the end of the conversion sequence. in continuous conversion mode (scan = 1 in atdctl5) , scf is set at the end of the first conversion sequence. clear scf by writing to control register 5 (atdctl5) to initiate a new conversion sequence. when the fast flag clear enable bit, affc, is set, scf is cleared after the first result register is read. cc2?cc0 ? conversion counter bits this 3-bit value reflects the value of the conver sion counter pointer in either a 4-conversion or 8-conversion sequence. the pointer shows which channel is currently being converted and which result register will be written next. ccf7?ccf0 ? conversion complete flags each atd channel has a ccf flag. a ccf flag is set at the end of the conversion on that channel. clear a ccf flag by reading status register 1 with the flag set and then reading the result register of that channel. when the fast flag clear enable bit, affc, is set, reading the result register clears the associated ccf flag even if the status register has not been read. address: $0066 bit 7654321bit 0 read:scf0000cc2cc1cc0 write: reset:00000000 = unimplemented figure 16-9. atd status register 1 (atdstat1) address: $0067 bit 7654321bit 0 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: reset:00000000 = unimplemented figure 16-10. atd status register 2 (atdstat2) registers and reset initialization mc68hc812a4 data sheet, rev. 7 freescale semiconductor 205 16.6.8 atd test registers read: special modes only write: special modes only the test registers control various special modes which are used during manufacturing. in the normal modes, reads of the test register return 0 and writes have no effect. sar9?sar0 ? sar data bits reads of this byte return the current value in the sar. writes to this byte change the sar to the value written. bits sar9?sar2 reflect th e eight sar bits used during the resolution process for an 8-bit result. sar1 and sar0 are reserved to allow future derivatives to increase atd resolution to 10 bits. rst ? reset bit when set, this bit causes all registers and activity in the module to assume the same state as out of power-on reset (except for adpu bit in atdctl2, which remains set, allowing the atd module to remain enabled). tstout ? multiplex output of tst3?tst0 (factory use) tst3?tst0 ? test bits 3 to 0 (reserved) selects one of 16 reserved factory testing modes address: $0068 bit 7654321bit 0 read: sar9 sar8 sar7 sar6 sar5 sar4 sar3 sar2 write: reset:00000000 figure 16-11. atd test register 1 (atdtest1) address: $0069 bit 7654321bit 0 read: sar1 sar0 rst tstout tst3 tst2 tst1 tst0 write: reset:00000000 figure 16-12. atd test register 2 (atdtest2) analog-to-digital converter (atd) mc68hc812a4 data sheet, rev. 7 206 freescale semiconductor 16.6.9 atd result registers read: anytime write: has no meaning or effect adrxh7?adrxh0 ? atd conversion result bits these bits contain the left justified, unsigned result from the atd conversion. the channel from which this result was obtained depends on the conver sion mode selected. these registers are always read-only in normal mode. 16.7 low-power options this section describes the three low-power modes: run mode wait mode stop mode 16.7.1 run mode clearing the atd power-up bit, adpu, in atd control register 2 (atdctl2) reduces power consumption in run mode. atd registers are still accessible, but the clock to the atd is disabled and atd analog circuits are powered down. 16.7.2 wait mode atd operation in wait mode depends on the state of the atd stop in wait bit, awai, in atd control register 2 (atdctl2). if awai is clear, the atd operates normally when the cpu is in wait mode if awai is set, the atd clock is disabled and conversion continues unless aswai bit in atdctl2 register is set. address: adr0h: adr1h: adr2h: adr3h: adr4h: adr5h: adr6h: adr7h: $0070 $0072 $0074 $0076 $0078 $007a $007c $007e bit 7654321bit 0 read: adrxh7 adrxh6 adrxh5 adrx h4 adrxh3 adrxh2 adrxh1 adrxh0 write: reset: indeterminate = unimplemented figure 16-13. atd result registers (adr0h?adr7h) interrupt sources mc68hc812a4 data sheet, rev. 7 freescale semiconductor 207 16.7.3 stop mode the atd is inactive in stop mode for reduced power consumption. the stop instruction aborts any conversion sequence in progress. 16.8 interrupt sources note the ascif flag is set only when a conversion sequence is completed and ascie = 1 or interrupts on the analog-to-digital converter (atd) module are enabled. 16.9 general-purpose ports port ad is an input-only port. when the atd is enabled, port ad is the analog input port for the atd. setting the atd power-up bit, adpu, in atd control register 2 enables the atd. port ad is available for general-purpose input when t he atd is disabled. cleari ng the adpu bit disables the atd. 16.10 port ad data register read: anytime; reads return logic levels on the pad pins write: has no meaning or effect pad7?pad0 ? port ad data input bits table 16-5. atd interrupt sources interrupt source flag local enable ccr mask vector address conversion sequence complete ascif ascie i bit $ffd2, $ffd3 address: $006f bit 7654321bit 0 read: pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 write: reset:00000000 = unimplemented figure 16-14. port ad data input register (portad) analog-to-digital converter (atd) mc68hc812a4 data sheet, rev. 7 208 freescale semiconductor 16.11 using the atd to me asure a potentiometer signal this exercise allows the student to utilize the at d on the hc12 to measure a potentiometer signal output routed from the udlp1 board to the hc12 atd pin pad6. first the atdctl registers are initialized. a delay loop of 100 s is then executed. the resolution is set up followed by a conversion set up on channel 6. after waiting for the status bit to set, the result goes to the d accumulator. if the program is working properly, a different value should be found in the d accumulator as the left potentiometer is varied for each execution of the program. 16.11.1 equipment for this exercise, use the m68hc812a4evb emulation board. 16.11.2 code listing note a comment line is delimited by a semicolon. if there is no code before comment, a semicolon (;) must be placed in the first column to avoid assembly errors. ; ---------------------------------------------------------------------- ; main program ; ---------------------------------------------------------------------- org $7000 ; 16k on-board ram, user code data area, ; start main program at $7000 main: bsr init ; branch to init subroutine to initialize atd bsr convert ; branch to convert subroutine for conversion done: bra done ; branch to self, convenient place for breakpoint ; ---------------------------------------------- ; subroutine init: initialize atd ; ; ---------------------------------------------- init: ldaa #$80 ; allow atd to function normally, staa atdctl2 ; atd flags clear normally & disable interrupts bsr delay ; delay (100 us) for wait delay time. ldaa #$00 ; select continue conversion in bgnd mode staa atdctl3 ; ignore freeze in atdctl3 ldaa #$01 ; select final sample time = 2 a/d clocks staa atdctl4 ; prescaler = div by 4 (prs4:0 = 1) rts ; return from subroutine using the atd to measure a potentiometer signal mc68hc812a4 data sheet, rev. 7 freescale semiconductor 209 ; ---------------------------------------------- ; subroutine convert: ; ; ---------------------------------------------- ; set-up atd, make single conversion and store the result to a memory location. ; configure and start a/d conversion ; analog input signal: on port ad6 ; convert: using single channel, non-continuous ; the result will be located in adr2h convert: ldaa #$06 ; initializes atd scan=0,mult=0, pad6, ; ; write clears flag staa atdctl5 ; 4 conversions on a single conversion ; ; sequence, wtconv: brclr atdstath,#$80,wtconv; wait for sequence complete flag ldd adr2h ; loads conversion result(adr2h) ; ; into accumulator bra convert ; continuously updates results rts ; return from subroutine ;* ------------------------------- ;* subroutine delay 100 us * ;* ------------------------------- ; delay required for atd converter to stabilize (100 usec) ldaa #$c8 ; load accumulator with "100 usec delay value" delay: deca ; decrement acc bne delay ; branch if not equal to zero rts ; return from subroutine end ; end of program analog-to-digital converter (atd) mc68hc812a4 data sheet, rev. 7 210 freescale semiconductor mc68hc812a4 data sheet, rev. 7 freescale semiconductor 211 chapter 17 development support 17.1 introduction this section describes: instruction queue queue tracking signals background debug mode (bdm) instruction tagging 17.2 instruction queue the cpu12 instruction queue provides at least three bytes of program information to the cpu when instruction execution begins. the cpu12 always co mpletely finishes executing an instruction before beginning to execute the next instruction. status signals ipipe[1:0] provide information about data movement in the queue and indicate when the cpu begins to execute instructions. this makes it possible to monitor cpu activity on a cycl e-by-cycle basis for debugging. information available on the ipipe[1:0] pins is time multiplexed. external circuitry can latch data movement information on rising edges of the e-clock signal; execution start inform ation can be latched on falling edges. table 17-1 shows the meaning of data on the pins. table 17-1. ipipe decoding data movement ? ipipe[1:0] captur ed at rising edge of e clock (1) 1. refers to data that was on the bus at the previous e falling edge. ipipe[1:0] mnemonic meaning 0:0 ? no movement 0:1 lat latch data from bus 1:0 ald advance queue and load from bus 1:1 all advance queue and load from latch execution start ? ipipe[1:0] captured at falling edge of e clock (2) 2. refers to bus cycle starti ng at this e falling edge. ipipe[1:0] mnemonic meaning 0:0 ? no start 0:1 int start interrupt sequence 1:0 sev start even instruction 1:1 sod start odd instruction development support mc68hc812a4 data sheet, rev. 7 212 freescale semiconductor program information is fetched a few cycles before it is used by the cpu. to monitor cycle-by-cycle cpu activity, it is necessary to externally reconstruct w hat is happening in the instruction queue. internally, the mcu only needs to buffer the data from program fetc hes. for system debug, it is necessary to keep the data and its associated address in the reconstructed instruction queue. the raw signals required for reconstruction of the queue are addr, data, r/w , eclk, and status signals ipipe[1:0]. the instruction queue consists of two 16-bit queue st ages and a holding latch on the input of the first stage. to advance the queue means to move the word in the first stage to the second stage and move the word from either the holding latch or the data bus input buffer into the first stage. to start even (or odd) instruction means to execute the opcode in the high-order (or low-order) byte of the second stage of the instruction queue. 17.3 background debug mode (bdm) background debug mode (bdm) is used for: system development in-circuit testing field testing programming bdm is implemented in on-chip hardware and provides a full set of debug options. because bdm control logic does not reside in the cpu, bdm hardware commands can be executed while the cpu is operating normally. the control logic generally uses cpu dead cycles to execute these commands, but can steal cycles fr om the cpu when necessary. other bdm commands are firmware based and require the cpu to be in active background mode for execution. while bdm is active, the cpu executes a firmware program located in a small on-ch ip rom that is available in the standard 64-kbyte memory map only while bdm is active. the bdm control logic communicates with an exter nal host development system serially, via the bkgd pin. this single-wire approach minimizes the number of pins needed for development support. 17.3.1 bdm serial interface the bdm serial interface requires the external controller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external c ontroller provides this falling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an external controller or by the mcu. data is transferred msb first at 16 e-clock cycles per bit ( nominal speed). the interface times out if 512 e-clock cycles occur between falling edges from the host. the hardware clears the command register when this timeout occurs. the bkgd pin can receive a high or low level or trans mit a high or low level. the following diagrams show timing for each of these cases. interface timing is synchronous to mcu clocks but asynchronous to the external host. the internal clock signal is shown for reference in counting cycles. background debug mode (bdm) mc68hc812a4 data sheet, rev. 7 freescale semiconductor 213 figure 17-1 shows an external host transmitting a logic 1 or 0 to the bkgd pin of a target m68hc12 mcu. the host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target e cycles later, the target senses the bit level on the bkgd pin. typically, the host actively drives the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. since the target does not drive the bkgd pin during this period, there is no need to treat the line as an open-drain signal during host-to-target transmissions. figure 17-1. bdm host-to-target serial bit timing figure 17-2 shows the host receiving a logic 1 from the target mc68hc812a4 mcu. since the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target e cycles). the host must release the low drive before the target mcu drives a brief active-high speed-up pulse seven cycles after the perceived start of the bit time. the host should sample the bit level about 10 cycles after it started the bit time. figure 17-3 shows the host receiving a logic 0 from the target mc68hc812a4 mcu. since the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target mcu. the host initiates the bit time but the target mc68hc812a4 finishes it. since the target want s the host to receive a logic 0, it drives the bkgd pin low for 13 e-clock cycles, then briefly drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. 17.3.2 enabling bdm firmware commands bdm is available in all operating modes, but mu st be made active before firmware commands can be executed. bdm is enabled by setting the enbdm bit in the bdm status register via the single wire interface (using a hardware command; write_bd_byte at $ff01). bdm must then be activated to map bdm registers and rom to addresses $ff00 to $ ffff and to put the mcu in active background mode. after the firmware is enabled, bdm can be activa ted by the hardware background command, by the bdm tagging mechanism, or by the cpu bgnd instructi on. an attempt to activate bdm before firmware has been enabled causes the mcu to resume normal instruction execution after a brief delay. earliest start target senses bit level 10 cycles synchronization uncertainty e clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time of next bit development support mc68hc812a4 data sheet, rev. 7 214 freescale semiconductor figure 17-2. bdm target-to-host serial bit timing (logic 1) figure 17-3. bdm target-to-host serial bit timing (logic 0) host samples bkgd pin 10 cycles e-clock target mcu host drive to bkgd pin target mcu speed-up pulse perceived start of bit time high-impedance high-impedance high-impedance bkgd pin r-c rise 10 cycles earliest start of next bit 10 cycles e-clock target mcu host drive to bkgd pin target mcu drive and perceived start of bit time high-impedance bkgd pin 10 cycles speed-up pulse speed-up pulse earliest start of next bit host samples bkgd pin background debug mode (bdm) mc68hc812a4 data sheet, rev. 7 freescale semiconductor 215 bdm becomes active at the next instruction boundary following executio n of the bdm background command, but tags activate bdm before a tagged instruction is executed. in special single-chip mode, background operation is enabled and active immediately out of reset. this active case replaces the m68hc11 boot function an d allows programming a system with blank memory. while bdm is active, a set of bdm control registers are mapped to addresses $ff00 to $ff06. the bdm control logic uses these registers which can be read anytime by bdm logic, not user programs. refer to 17.4 bdm registers for detailed descriptions. some on-chip peripherals have a bdm control bit whic h allows suspending the peripheral function during bdm. for example, if the timer control is enabled, t he timer counter is stopped while in bdm. once normal program flow is continued, the timer counter is re-enabled to simulate real-time operations. 17.3.3 bdm commands all bdm command opcodes are eight bits long and can be followed by an address and/or data, as indicated by the instruction. these commands do not require the cpu to be in active bdm mode for execution. the host controller must wait 150 cycles for a non- intrusive bdm command to execute before another command can be sent. this delay includes 128 cycles for the maximum delay for a dead cycle. for data read commands, the host must insert this delay between sending the address and attempting to read the data. bdm logic retains control of the internal buses unti l a read or write is completed. if an operation can be completed in a single cycle, it does not intrude on normal cpu operation. however, if an operation requires multiple cycles, cpu clocks ar e frozen until the operation is complete. the cpu must be in background mode to execute co mmands that are implemented in the bdm rom. the bdm rom is located at $ff20 to $ffff while bd m is active. there are also seven bytes of bdm registers which are located at $ff00 to $ff06 whil e bdm is active. the cpu executes code from this rom to perform the requested operati on. these commands are shown in table 17-2 and table 17-3 . table 17-2. bdm commands implemented in hardware command opcode (hex) data description background 90 none enter background mode, if firmware is enabled. read_bd_byte e4 16-bit address 16-bit data out read from memory with bdm in map (may steal cycles if external access); data for odd address on low byte, data for even address on high byte status (1) e4 ff01, 0000 0000 (out) read_bd_byte $ff01. running user code; bgnd instruction is not allowed ff01, 1000 0000 (out) read_bd_byte $ff01. bgnd instruction is allowed. ff01, 1100 0000 (out) read_bd_byte $ff01. background mode active, waiting for single wire serial command read_bd_word ec 16-bit address 16-bit data out read from memory with bdm in map (may steal cycles if external access); must be aligned access read_byte e0 16-bit address 16-bit data out read from memory with bdm out of map (may steal cycles if external access); data for odd address on low byte, data for even address on high byte development support mc68hc812a4 data sheet, rev. 7 216 freescale semiconductor read_word e8 16-bit address 16-bit data out read from memory with bdm out of map (may steal cycles if external access); must be aligned access write_bd_byte c4 16-bit address 16-bit data in write to memory with bdm in map (may steal cycles if external access); data for odd address on low byte, data for even address on high byte enable_ firmware (2) c4 ff01, 1xxx xxxx (in) write byte $ff01, set the enbdm bit. this allows execution of commands which are implemented in firmware. typically, read status, or in the msb, write the result back to status. write_bd_word cc 16-bit address 16-bit data in write to memory with bdm in map (may steal cycles if external access); must be aligned access write_byte c0 16-bit address 16-bit data in write to memory with bdm out of map (may steal cycles if external access); data for odd address on low byte, data for even address on high byte write_word c8 16-bit address 16-bit data in write to memory with bdm out of map (may steal cycles if external access); must be aligned access 1. status command is a specific case of the read_bd_byte command. 2. enable_firmware is a specific case of the write_bd_byte command. table 17-3. bdm firmware commands command opcode (hex) data description read_next 62 16-bit data out x = x + 2; read next word pointed to by x read_pc 63 16-bit data out read program counter read_d 64 16-bit data out read d accumulator read_x 65 16-bit data out read x index register read_y 66 16-bit data out read y index register read_sp 67 16-bit data out read stack pointer write_next 42 16-bit data in x = x + 2; write next word pointed to by x write_pc 43 16-bit data in write program counter write_d 44 16-bit data in write d accumulator write_x 45 16-bit data in write x index register write_y 46 16-bit data in write y index register write_sp 47 16-bit data in write stack pointer go 08 none go to user program trace1 10 none execute one user instruction, then return to bdm taggo 18 none enable tagging and go to user program table 17-2. bdm commands implemented in hardware (continued) command opcode (hex) data description bdm registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 217 17.4 bdm registers seven bdm registers are mapped into the standard 64-kbyte address space when bdm is active. the registers can be accessed with the hardware r ead_bd and write_bd commands, but must not be written during bdm operation. most users are only interested in the status register at $ff01; other registers are for use only by bdm firmware and logic. the instruction register is discussed for two conditions: when a hardware command is executed when a firmware command is executed 17.4.1 bdm inst ruction register this section describes the bdm instruction register under hardware command and firmware command. 17.4.1.1 hardware command the bits in the bdm instruction register have the following meanings when a hardware command is executed. h/f ? hardware/firmware flag 1 = hardware instruction 0 = firmware instruction data ? data flag 1 = data included in command 0 = no data r/w ? read/write flag 0 = write 1 = read bkgnd ? hardware request bit to enter active background mode 1 = hardware background command (instruction = $90) 0 = not a hardware background command w/b ? word/byte transfer flag 1 = word transfer 0 = byte transfer bd/u ? bdm map/user map flag indicates whether bdm registers and rom are mapped to addresses $ff00 to $ffff in the standard 64-kbyte address space. used only by hardware read/write commands. 1 = bdm resources in map 0 = bdm resources not in map address: $ff00 bit 7654321bit 0 read: h/f data r/w bkgnd w/b bd/u 0 0 write: reset:00000000 figure 17-4. bdm instruction register (instruction) development support mc68hc812a4 data sheet, rev. 7 218 freescale semiconductor 17.4.1.2 firmware command the bits in the bdm instruction register have the following meanings when a firmware command is executed. h/f ? hardware/firmware flag 1 = hardware control logic 0 = firmware control logic data ? data flag 1 = data included in command 0 = no data r/w ? read/write flag 1 = read 0 = write ttago ? trace, tag, and go field regn ? register/next field indicates which register is being affected by a command. in the case of a read_next or write_next command, index register x is pre-increm ented by 2 and the word pointed to by x is then read or written. address: $ff00 bit 7654321bit 0 read: h/f data r/w ttago regn write: reset:00000000 figure 17-5. bdm instruction register (instruction) table 17-4. ttago decoding ttago value instruction 00 ? 01 go 10 trace1 11 taggo table 17-5. regn decoding regn value instruction 000 ? 001 ? 010 read/write next 011 pc 100 d 101 x 110 y 111 sp bdm registers mc68hc812a4 data sheet, rev. 7 freescale semiconductor 219 17.4.2 bdm status register this register can be read or wri tten by bdm commands or firmware. enbdm ? enable bdm bit (permit active background debug mode) 1 = bdm can be made active to allow firmware commands. 0 = bdm cannot be made active (hardware commands still allowed). bdmact ? background mode active status bit 1 = bdm active and waiting for serial commands 0 = bdm not active entag ? instruction tagging enable bit set by the taggo instruction and cleared when bdm is entered. 1 = tagging active (bdm cannot process se rial commands while tagging is active.) 0 = tagging not enabled or bdm active sdv ? shifter data valid bit shows that valid data is in the serial interface shift register. used by firmware-based instructions. 1 = valid data 0 = no valid data trace ? asserted by the trace1 instruction 17.4.3 bdm shift register this 16-bit register contains data being rece ived or transmitted via the serial interface. address: $ff01 bit 76 54321bit 0 read: enbdm edmact entag sdv trace 0 0 0 write: reset:0 0 000000 single-chip peripheral:1 0 000000 figure 17-6. bdm status register (status) address: $ff02 bit 7654321bit 0 read: s15 s14 s13 s12 s11 s10 s9 s8 write: reset:00000000 address: $ff03 bit 7654321bit 0 read: s7 s6 s5 s4 s3 s2 s1 s0 write: reset:00000000 figure 17-7. bdm shift register (shifter) development support mc68hc812a4 data sheet, rev. 7 220 freescale semiconductor 17.4.4 bdm address register this 16-bit register is temporary storage for bdm hardware and firmware commands. 17.4.5 bdm ccr holding register this register preserves the content of the cpu12 ccr while bdm is active. 17.5 instruction tagging the instruction queue and cycle-by-cycle cpu activity can be reconstructed in real time or from trace history that was captured by a logic analyzer. however, the reconstructed queue cannot be used to stop the cpu at a specific instruction, because execution has already begun by the time an operation is visible outside the mcu. a separate instruction tagging mechanism is provided for this purpose. executing the bdm taggo command configures two mcu pins for tagging. tagging information is latched on the falling edge of eclk along with program information as it is fetched. tagging is allowed in all modes. tagging is disabled when bdm becomes active and bdm serial commands cannot be processed while tagging is active. taghi is a shared function of the bkgd pin. taglo is a shared function of the pe3/lstrb pin, a multiplexed i/o pin. for 1/4 cycle before and after the rising edge of the e-clock, this pin is the lstrb driven output. taglo and taghi inputs are captured at the falling edge of the e-clock. a logic 0 on taghi and/or taglo marks (tags) the instruction on the high and/or low byte of the program word that was on the data bus at the same falling edge of the e-clock. the tag follows the information in the queue as the queue is advanced. when a tagged instruction reaches the head of the queue, the cpu enters acti ve background debugging mode rather than executing the instruction. this is the mechanism by which a development system initiates hardware breakpoints. address: $ff04 bit 7654321bit 0 read: a15 a14 a13 a12 a11 a10 a9 a8 write: reset:00000000 address: $ff05 bit 7654321bit 0 read: a7 a6 a5 a4 a3 a2 a1 a0 write: reset:00000000 figure 17-8. bdm address register (address) address: $ff06 bit 7654321bit 0 read: ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 write: reset:00000000 figure 17-9. bdm ccr holding register (ccrsav) mc68hc812a4 data sheet, rev. 7 freescale semiconductor 221 chapter 18 electrical characteristics 18.1 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 18.4 dc electrical characteristics for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd ). rating symbol value unit supply voltage v dd v dda v ddx ?0.3 to +6.5 v input voltage v in ?0.3 to +6.5 v maximum current per pin excluding v dd and v ss i in 25 ma storage temperature t stg ?55 to +150 c v dd differential voltage v dd ?v ddx 6.5 v electrical characteristics mc68hc812a4 data sheet, rev. 7 222 freescale semiconductor 18.2 functional operating range 18.3 thermal characteristics rating symbol value unit operating temperature range (1) mc68hc812a4pv8 mc68hc812a4cpv8 1. for additional information, refer to the technical supplement document for 3.3 volt specifications (mc68c812a4) . this supplement can be found at http://freescale.com t a t l to t h 0 to + 70 ? 40 to + 85 c operating voltage range v dd 5.0 10% v characteristic symbol value unit average junction temperature t j t a + (p d ja ) c ambient temperature t a user-determined c package thermal resistance (junction-to-ambient) 112-pin thin quad flat pack (tqfp) ja 39 c/w total power dissipation (1) 1. this is an approximate value, neglecting p i/o . p d p int + p i/o or w device internal power dissipation p int i dd v dd w i/o pin power dissipation (2) 2. for most applications, p i/o ? p int and can be neglected. p i/o user-determined w a constant (3) 3. k is a constant pertaining to the device. solve for k with a known t a and a measured p d (at equilibrium). use this value of k to solve for p d and t j iteratively for any value of t a . k p d (t a + 273 c) + ja p d 2 w/ c k t j 273 c + -------------------------- - dc electrical characteristics mc68hc812a4 data sheet, rev. 7 freescale semiconductor 223 18.4 dc electrical characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min max unit input high voltage, all inputs v ih 0.7 v dd v dd + 0.3 v input low voltage, all inputs v il v ss ? 0.3 0.2 v dd v output high voltage, all i/o and output pins normal drive strength i oh = ? 10.0 a i oh = ? 0.8 ma reduced drive strength i oh = ? 4.0 a i oh = ? 0.3 ma v oh v dd ? 0.2 v dd ? 0.8 v dd ? 0.2 v dd ? 0.8 ? ? ? ? v output low voltage, all i/o and output pins, normal drive strength i ol = 10.0 a i ol = 1.6 ma extal, pad[7:0], v rh , v rl , v fp , xirq , reduced drive strength i ol = 3.6 a i ol = 0.6 ma v ol ? ? ? ? v ss + 0.2 v ss + 0.4 v ss + 0.2 v ss + 0.4 v input leakage current (2) all input pins v in = v dd or v ss ? v rl , v rh , pad6?pad0 v in = v dd or v ss ? irq v in = v dd or v ss ? pad7 2. specification is for parts in the ?40 to + 85c range. higher temperature ranges will result in increased current leakage. i in ? ? ? 1 10 10 a three-state leakage, i/o ports, bkgd, and reset i oz ? 2.5 a input capacitance all input pins and atd pins (non-sampling) atd pins (sampling) all i/o pins c in ? ? ? 10 15 20 pf output load capacitance all outputs except ps7?ps4 ps7?ps4 c l ? ? 90 200 pf active pullup, pulldown current irq , xirq , dbe , eclk, lstrb , r/w , and bkgd ports a, b, c, d, f, g, h, j, p, s, and t i apu 50 500 a ram standby voltage, power down v sb 1.5 ? v ram standby current i sb ?10 a electrical characteristics mc68hc812a4 data sheet, rev. 7 224 freescale semiconductor 18.5 supply current 18.6 atd maximum ratings characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol 8 mhz typical 2 mhz 4 mhz 8 mhz unit maximum total supply current run single-chip mode expanded mode wait, all peripheral functions shut down single-chip mode expanded mode stop, single-chip mode, no clocks ?40 c to +85 c +85 c to +105 c +105 c to +125 c i dd wi dd si dd 30 47 7 8 < 1 < 10 < 25 15 25 1.5 4 10 25 50 25 40 4 5 10 25 50 40 65 8 10 10 25 50 ma ma ma ma a a a maximum power dissipation (2) single-chip mode expanded mode 2. includes i dd and i dda p d 54 76 62 90 54 76 62 90 mw mw characteristic symbol value units atd reference voltage v rh v dda v rl v ssa v rh v rl ? 0.3 to + 6.5 ? 0.3 to + 6.5 v v ss differential voltage | v ss ? v ssa | 0.1 v v dd differential voltage | v dd ? v dda | v dd ? v ddx 6.5 6.5 v v ref differential voltage | v rh ? v rl | 6.5 v reference to supply differential voltage | v rh ? v dda | | v rl ? v ssa | 6.5 6.5 v atd dc electrical characteristcs mc68hc812a4 data sheet, rev. 7 freescale semiconductor 225 18.7 atd dc elect rical characteristcs 18.8 analog converter operating characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz, unless otherwise noted symbol min max unit analog supply voltage v dda 4.5 5.5 v analog supply current, normal operation i dda ?1.0ma reference voltage, low v rl v ssa v dda / 2 v reference voltage, high v rh v dda / 2v dda v v ref differential reference voltage (2) 2. accuracy is guaranteed at v rh ? v rl = 5.0 vdc 10% . v rh ? v rl 4.5 5.5 v input voltage (3) 3. to obtain full-scale, full-range results, v ssa v rl v indc v rh v dda . v indc v ssa v dda v input current, off channel (4) 4. maximum leakage occurs at maximum operating temperature. cu rrent decreases by approximately one-half for each 10 c decrease from maximum temperature. i off ?100na reference supply current i ref ?250 a input capacitance not sampling sampling c inn c ins ? ? 10 15 pf characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz, unless otherwise noted symbol min typical max unit 8-bit resolution (2) 2. v rh ? v rl 5.12 v; v dda ?v ssa = 5.12 v 2 counts ? 24 ? mv differential non-linearity (3) 3. at v ref = 5.12 v, one 8-bit count = 20 mv. dnl ? 0.5 ? + 0.5 count integral non-linearity (3) inl ? 1? + 1 count absolute error (3),(4) 2, 4, 8, and 16 atd sample clocks 4. 8-bit absolute error of 1 count (20 mv) includes 1/2 count (10 mv) inherent quantiz ation error and 1/2 count (10 mv) circuit (differential, integral, and offset) error. ae ? 2? + 2 count maximum source impedance r s ?20 see note (5) 5. maximum source impedance is application-dependent. error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. error from junction leakage is a function of external source impedance and input leakage current. expected error in result value due to junction leakage is expressed in voltage (v errj ): v errj = r s i off where i off is a function of operating temperature. charge-sharing effects with internal capacit ors are a function of atd clock speed, the number of channels being scanned, and sour ce impedance. for 8-bit conversions, charge pump leakage is computed as follows: v errj = .25 pf v dda r s atdclk/(8 number of channels) k ? electrical characteristics mc68hc812a4 data sheet, rev. 7 226 freescale semiconductor 18.9 atd ac operating characteristics 18.10 eeprom characteristics characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , atd clock = 2 mhz, unless otherwise noted symbol min max unit atd operating clock frequency f at d c l k 0.5 2.0 mhz conversion time per channel 0.5 mhz f at d c l k 2 mhz 18 atd clocks 32 atd clocks t conv 8.0 15.0 32.0 60.0 s stop recovery time v dda = 5.0 v t sr ?50 s characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min typical max unit minimum programming clock frequency (2) 2. rc oscillator must be enabled if programming is desired and f sys < f prog . f prog 4.0 ? ? mhz programming time t prog 10.0 ? 10.5 ms clock recovery time following stop, to continue programming t crstop ?? t prog + 1 ms erase time t erase 10.0 ? 10.5 ms write/erase endurance ? 10,000 30,000 (3) 3. if average t h is below 85 c ? cycles data retention ? 10 ? ? years control timing mc68hc812a4 data sheet, rev. 7 freescale semiconductor 227 18.11 control timing figure 18-1. timer inputs characteristic symbol 8.0 mhz unit min max frequency of operation f o dc 8.0 mhz e-clock period t cyc 125 ? ns crystal frequency f xtal ?16.0mhz external oscillator frequency 2 f o dc 16.0 mhz processor control setup time t pcsu = t cyc / 2 + 30 t pcsu 82 ? ns reset input pulse width to guarantee external reset vector minimum input time (can be pre-empted by internal reset) pw rstl 32 2 ? ? t cyc mode programming setup time t mps 4? t cyc mode programming hold time t mph 10 ? ns interrupt pulse width, irq , edge-sensitive mode, kwu pw irq = 2 t cyc + 20 pw irq 270 ? ns wait recovery startup time t wrs ?4t cyc timer pulse width, input capture pulse accumulator input pw tim = 2 t cyc + 20 pw tim 270 ? ns pt7 (2) pt7 (1) pt[7:0] (2) pt[7:0] (1) notes: 1. rising edge-sensitive input 2. falling edge-sensitive input pw tim pw pa mc68hc812a4 data sheet, rev. 7 228 freescale semiconductor electrical characteristics figure 18-2. por and external reset timing diagram t pcsu internal moda, modb eclk extal v dd reset 4098 t cyc free fffe fffe 3rd 1st 2nd free fffe fffe fffe t mph pw rstl t mps address pipe pipe pipe 1st exec 3rd pipe 2nd pipe 1st pipe 1st exec note: reset timing is subject to change. mc68hc812a4 data sheet, rev. 7 freescale semiconductor 229 control timing figure 18-3. stop recovery timing diagram pw irq t stopdelay (3) irq 1 irq or xirq eclk 1st address 4 sp-9 free free vector free free resume program with instruction which follows the stop instruction. internal address 5 clocks notes: 1. edge-sensitive irq pin (irqe bit = 1) 2. level-sensitive irq pin (irqe bit = 0) 3. t stopdelay = 4098 t cyc if dly bit = 1 or 2 t cyc if dly = 0. 4. xirq with x bit in ccr = 1. 5. irq or (xirq with x bit in ccr = 0) opt 1st 2nd 3rd 1st exec pipe pipe exec sp-8 sp-6 fetch pipe sp-6 sp-8 sp-9 mc68hc812a4 data sheet, rev. 7 230 freescale semiconductor electrical characteristics figure 18-4. wait recovery timing diagram figure 18-5. interrupt timing diagram t pcsu pc, iy, ix, b:a, , ccr stack registers eclk r/w address irq , xirq , or internal interrupts sp ? 2 sp ? 4 sp ? 6 . . . sp ? 9 sp ? 9 sp ? 9. . . sp ? 9 sp ? 9 vector free 1st 2nd 3rd pipe t wrs note: reset also causes recovery from wait. address pipe pipe 1st exec eclk pw irq 1st 3rd address irq (1) sp ? 9 t pcsu irq (2) , xirq , or internal interrupt vector sp ? 2 1st sp ? 4 sp ? 6 2nd sp ? 8 data vect pc iy ix b:a ccr prog r/w notes: 1. edge sensitive irq pin (irqe bit = 1) 2. level sensitive irq pin (irqe bit = 0) fetch addr exec pipe pipe pipe prog fetch prog fetch peripheral port timing mc68hc812a4 data sheet, rev. 7 freescale semiconductor 231 18.12 peripheral port timing figure 18-6. port read timing diagram figure 18-7. port write timing diagram characteristic symbol 8.0 mhz unit min max frequency of operation (e-clock frequency) f o dc 8.0 mhz e-clock period t cyc 125 ? ns peripheral data setup time, mcu read of ports t pdsu = t cyc / 2 + 30 t pdsu 102 ? ns peripheral data hold time, mcu read of ports t pdh 0?ns delay time, peripheral data write, mcu write to ports t pwd ?40ns eclk mcu read of port ports t pdsu t pdh eclk mcu write to port previous port data new data valid port a t pwd electrical characteristics mc68hc812a4 data sheet, rev. 7 232 freescale semiconductor 18.13 non-multiplexe d expansion bus timing num characteristic (1), (2) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted 2. all timings are calculated for normal port drives. delay symbol 8 mhz unit min max frequency of operation (e-clock frequency) ? f o dc 8.0 mhz 1 cycle timet cyc = 1 / f o t cyc 125 ? ns 2 pulse width, e lowpw el = t cyc / 2 + delay ? 2 pw el 60 ? ns 3 pulse width, e high (3) pw eh = t cyc / 2 + delay 3. this characteristic is affected by clock stretch. add n t cyc where n = 0, 1, 2, or 3, depending on the number of clock stretches. ? 2 pw eh 60 ? ns 5 address delay timet ad = t cyc / 4 + delay 29 t ad ?60ns 6 address hold time ? t ah 20 ? ns 7 address valid time to e riset av = pw el ? t ad ? t av 0?ns 11 read data setup time ? t dsr 30 ? ns 12 read data hold time ? t dhr 0?ns 13 write data delay time (4) t ddw = t cyc / 4 + delay 4. equation still under evaluation 25 t ddw ?46ns 14 write data hold time ? t dhw 20 ? ns 15 write data setup time (3) t dsw = pw eh ? t ddw ? t dsw 30 ? ns 16 read/write delay timwt rwd = t cyc / 4 + delay 18 t rwd ?49ns 17 read/write valid time to e riset rwv = pw el ? t rwd ? t rwv 20 ? ns 18 read/write hold time ? t rwh 20 ? ns 19 low strobe delay timet lsd = t cyc / 4 + delay 18 t lsd ?49ns 20 low strobe valid time to e riset lsv = pw el ? t lsd ? t lsv 11 ? ns 21 low strobe hold time ? t lsh 20 ? ns 22 address access time (3) t acca = t cyc ? t ad ? t dsr ? t acca ?35ns 23 access time from e rise (3) t acce = pw eh ? t dsr ? t acce ?30ns 26 chip-select delay timet csd = t cyc / 4 + delay 29 t csd ?60ns 27 chip-select access time (3) t accs = t cyc ? t csd ? t dsr ? t accs ?65ns 28 chip-select hold time ? t csh 010ns 29 chip-select negated timet csn = t cyc / 4 + delay 5t csn 36 ? ns non-multiplexed expansion bus timing mc68hc812a4 data sheet, rev. 7 freescale semiconductor 233 figure 18-8. non-multiplexed expansion bus timing diagram eclk r/w 1 6 data[15:0] data[15:0] 2 3 18 22 11 12 13 14 addr[15:0] note: measurement points shown are 20% and 70% of v dd . 5 15 cs 16 27 28 17 read write 23 lstrb 21 19 20 (w/o tag enabled) 26 29 7 electrical characteristics mc68hc812a4 data sheet, rev. 7 234 freescale semiconductor 18.14 spi timing num function (1), (2) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , 200 pf load on all spi pins 2. all ac timing is shown with respect to 20% v dd and 70% v dd levels, unless otherwise noted. symbol min max unit operating frequency master slave f op dc dc 1 / 2 1 / 2 e-clock frequency 1 sck period master slave t sck 2 2 256 ? t cyc 2 enable lead time master slave t lead 1 / 2 1 ? ? t sck t cyc 3 enable lag time master slave t lag 1 / 2 1 ? ? t sck t cyc 4 clock (sck) high or low time master slave t wsck t cyc ? 60 t cyc ? 30 128 t cyc ? ns 5 sequential transfer delay master slave t td 1 / 2 1 ? ? t sck t cyc 6 data setup time (inputs) master slave t su 30 30 ? ? ns 7 data hold time (inputs) master slave t hi 0 30 ? ? ns 8 slave access time t a ?1 t cyc 9 slave miso disable time t dis ?1 t cyc 10 data valid (after sck edge) master slave t v ? ? 50 50 ns 11 data hold time (outputs) master slave t ho 0 0 ? ? ns 12 rise time input output t ri t ro ? ? t cyc ? 30 30 ns ns 13 fall time input output t fi t fo ? ? t cyc ? 30 30 ns ns spi timing mc68hc812a4 data sheet, rev. 7 freescale semiconductor 235 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) figure 18-9. spi timing diagram (sheet 1 of 2) sck (output sck output miso input mosi output ss (1) output 1 10 6 7 msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 11 4 4 2 10 cpol = 0 cpol = 1 5 3 12 13 1. ss output mode (dds7 = 1, ssoe = 1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb notes: sck output sck output miso input mosi output 1 6 7 msb in (2) bit 6 . . . 1 lsb in master msb out (2) master lsb out bit 6 . . . 1 4 4 10 12 13 11 port data cpol = 0 cpol = 1 port data ss (1) output 5 2 13 12 3 1. ss output mode (dds7 = 1, ssoe = 1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb notes: electrical characteristics mc68hc812a4 data sheet, rev. 7 236 freescale semiconductor a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) figure 18-9. spi timing diagram (sheet 2 of 2) sck input sck input mosi input miso output ss input 1 10 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 11 4 4 2 8 cpol = 0 cpol = 1 5 3 13 note: not defined but normally msb of character just received slave 13 12 11 see 12 note 9 sck input sck input mosi input miso output 1 6 7 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 10 12 13 11 see cpol = 0 cpol = 1 ss input 5 2 13 12 3 note: not defined but normally lsb of character just received slave note 8 9 mc68hc812a4 data sheet, rev. 7 freescale semiconductor 237 chapter 19 mechanical specifications 19.1 introduction this section provides dimensions for t he 112-lead low-profile quad flat pack (lqfp). 19.2 package dimensions refer to the following pages fo r detailed package dimensions. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2006. all rights reserved. mc68hc812a4 rev. 7, 05/2006 |
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